From b5fb73b6bed11aaa87919c3885349e6f1ca0349f Mon Sep 17 00:00:00 2001 From: Andrew Stubbs Date: Thu, 20 Feb 2020 14:44:04 +0000 Subject: [PATCH] amdgcn: Use correct offset mode for gather/scatter The scatter/gather pattern names changed for GCC 10, but I hadn't noticed. This switches the patterns to the new offset mode scheme. 2020-02-21 Andrew Stubbs gcc/ * config/gcn/gcn-valu.md (gather_load): Rename to ... (gather_loadv64si): ... this and set operand 2 to V64SI. (scatter_store): Rename to ... (scatter_storev64si): ... this and set operand 1 to V64SI. (scatter_exec): Delete. Move contents ... (mask_scatter_store): ... here, and rename that to ... (mask_gather_loadv64si): ... this. Set operand 2 to V64SI. Remove mode conversion. (mask_gather_load): Rename to ... (mask_scatter_storev64si): ... this. Set operand 1 to V64SI. Remove mode conversion. * config/gcn/gcn.c (gcn_expand_scaled_offsets): Remove mode conversion. --- gcc/ChangeLog | 15 +++++++++ gcc/config/gcn/gcn-valu.md | 78 +++++++++++++--------------------------------- gcc/config/gcn/gcn.c | 9 ------ 3 files changed, 36 insertions(+), 66 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d0c9f29..b6e5253 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,18 @@ +2020-02-21 Andrew Stubbs + + * config/gcn/gcn-valu.md (gather_load): Rename to ... + (gather_loadv64si): ... this and set operand 2 to V64SI. + (scatter_store): Rename to ... + (scatter_storev64si): ... this and set operand 1 to V64SI. + (scatter_exec): Delete. Move contents ... + (mask_scatter_store): ... here, and rename that to ... + (mask_gather_loadv64si): ... this. Set operand 2 to V64SI. + Remove mode conversion. + (mask_gather_load): Rename to ... + (mask_scatter_storev64si): ... this. Set operand 1 to V64SI. + Remove mode conversion. + * config/gcn/gcn.c (gcn_expand_scaled_offsets): Remove mode conversion. + 2020-02-21 Martin Jambor PR tree-optimization/93845 diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md index d5e6d0a..a0cc9a2 100644 --- a/gcc/config/gcn/gcn-valu.md +++ b/gcc/config/gcn/gcn-valu.md @@ -679,10 +679,10 @@ ;; fields normally found in a MEM. ;; - Multiple forms of address expression are supported, below. -(define_expand "gather_load" +(define_expand "gather_loadv64si" [(match_operand:VEC_ALLREG_MODE 0 "register_operand") (match_operand:DI 1 "register_operand") - (match_operand 2 "register_operand") + (match_operand:V64SI 2 "register_operand") (match_operand 3 "immediate_operand") (match_operand:SI 4 "gcn_alu_operand")] "" @@ -811,9 +811,9 @@ [(set_attr "type" "flat") (set_attr "length" "12")]) -(define_expand "scatter_store" +(define_expand "scatter_storev64si" [(match_operand:DI 0 "register_operand") - (match_operand 1 "register_operand") + (match_operand:V64SI 1 "register_operand") (match_operand 2 "immediate_operand") (match_operand:SI 3 "gcn_alu_operand") (match_operand:VEC_ALLREG_MODE 4 "register_operand")] @@ -833,34 +833,6 @@ DONE; }) -(define_expand "scatter_exec" - [(match_operand:DI 0 "register_operand") - (match_operand 1 "register_operand") - (match_operand 2 "immediate_operand") - (match_operand:SI 3 "gcn_alu_operand") - (match_operand:VEC_ALLREG_MODE 4 "register_operand") - (match_operand:DI 5 "gcn_exec_reg_operand")] - "" - { - operands[5] = force_reg (DImode, operands[5]); - - rtx addr = gcn_expand_scaled_offsets (DEFAULT_ADDR_SPACE, operands[0], - operands[1], operands[3], - INTVAL (operands[2]), operands[5]); - - if (GET_MODE (addr) == V64DImode) - emit_insn (gen_scatter_insn_1offset_exec (addr, const0_rtx, - operands[4], const0_rtx, - const0_rtx, - operands[5])); - else - emit_insn (gen_scatter_insn_2offsets_exec (operands[0], addr, - const0_rtx, operands[4], - const0_rtx, const0_rtx, - operands[5])); - DONE; - }) - ; Allow any address expression (define_expand "scatter_expr" [(set (mem:BLK (scratch)) @@ -2795,10 +2767,10 @@ DONE; }) -(define_expand "mask_gather_load" +(define_expand "mask_gather_loadv64si" [(match_operand:VEC_ALLREG_MODE 0 "register_operand") (match_operand:DI 1 "register_operand") - (match_operand 2 "register_operand") + (match_operand:V64SI 2 "register_operand") (match_operand 3 "immediate_operand") (match_operand:SI 4 "gcn_alu_operand") (match_operand:DI 5 "")] @@ -2806,16 +2778,6 @@ { rtx exec = force_reg (DImode, operands[5]); - /* TODO: more conversions will be needed when more types are vectorized. */ - if (GET_MODE (operands[2]) == V64DImode) - { - rtx tmp = gen_reg_rtx (V64SImode); - emit_insn (gen_truncv64div64si2_exec (tmp, operands[2], - gcn_gen_undef (V64SImode), - exec)); - operands[2] = tmp; - } - rtx addr = gcn_expand_scaled_offsets (DEFAULT_ADDR_SPACE, operands[1], operands[2], operands[4], INTVAL (operands[3]), exec); @@ -2836,9 +2798,9 @@ DONE; }) -(define_expand "mask_scatter_store" +(define_expand "mask_scatter_storev64si" [(match_operand:DI 0 "register_operand") - (match_operand 1 "register_operand") + (match_operand:V64SI 1 "register_operand") (match_operand 2 "immediate_operand") (match_operand:SI 3 "gcn_alu_operand") (match_operand:VEC_ALLREG_MODE 4 "register_operand") @@ -2847,18 +2809,20 @@ { rtx exec = force_reg (DImode, operands[5]); - /* TODO: more conversions will be needed when more types are vectorized. */ - if (GET_MODE (operands[1]) == V64DImode) - { - rtx tmp = gen_reg_rtx (V64SImode); - emit_insn (gen_truncv64div64si2_exec (tmp, operands[1], - gcn_gen_undef (V64SImode), - exec)); - operands[1] = tmp; - } + rtx addr = gcn_expand_scaled_offsets (DEFAULT_ADDR_SPACE, operands[0], + operands[1], operands[3], + INTVAL (operands[2]), exec); - emit_insn (gen_scatter_exec (operands[0], operands[1], operands[2], - operands[3], operands[4], exec)); + if (GET_MODE (addr) == V64DImode) + emit_insn (gen_scatter_insn_1offset_exec (addr, const0_rtx, + operands[4], const0_rtx, + const0_rtx, + exec)); + else + emit_insn (gen_scatter_insn_2offsets_exec (operands[0], addr, + const0_rtx, operands[4], + const0_rtx, const0_rtx, + exec)); DONE; }) diff --git a/gcc/config/gcn/gcn.c b/gcc/config/gcn/gcn.c index 531f47a..a8fd7d6 100644 --- a/gcc/config/gcn/gcn.c +++ b/gcc/config/gcn/gcn.c @@ -1861,15 +1861,6 @@ rtx gcn_expand_scaled_offsets (addr_space_t as, rtx base, rtx offsets, rtx scale, bool unsigned_p, rtx exec) { - /* Convert the offsets to V64SImode. - TODO: more conversions will be needed when more types are vectorized. */ - if (GET_MODE (offsets) == V64DImode) - { - rtx tmp = gen_reg_rtx (V64SImode); - emit_insn (gen_truncv64div64si2 (tmp, offsets)); - offsets = tmp; - } - rtx tmpsi = gen_reg_rtx (V64SImode); rtx tmpdi = gen_reg_rtx (V64DImode); rtx undefsi = exec ? gcn_gen_undef (V64SImode) : NULL; -- 2.7.4