From b5f8ac26829385d98f730c2a76c5f9a6306df2f8 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper@sifive.com>
Date: Thu, 27 May 2021 08:21:07 -0700
Subject: [PATCH] [X86] Pre-commit tests for D103192. NFC

---
 llvm/test/CodeGen/X86/vec_shift5.ll | 44 +++++++++++++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/llvm/test/CodeGen/X86/vec_shift5.ll b/llvm/test/CodeGen/X86/vec_shift5.ll
index c17ea3f..f6f9671 100644
--- a/llvm/test/CodeGen/X86/vec_shift5.ll
+++ b/llvm/test/CodeGen/X86/vec_shift5.ll
@@ -170,6 +170,50 @@ define <2 x i64> @test16() {
   ret <2 x i64> %1
 }
 
+; Make sure we fold fully undef input vectors. We previously folded only when
+; undef had a single use so use 2 undefs.
+define <4 x i32> @test17(<4 x i32> %a0, <4 x i32>* %dummy) {
+; X86-LABEL: test17:
+; X86:       # %bb.0:
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    pslld $6, %xmm0
+; X86-NEXT:    movdqa %xmm0, (%eax)
+; X86-NEXT:    pslld $7, %xmm0
+; X86-NEXT:    retl
+;
+; X64-LABEL: test17:
+; X64:       # %bb.0:
+; X64-NEXT:    pslld $6, %xmm0
+; X64-NEXT:    movdqa %xmm0, (%rdi)
+; X64-NEXT:    pslld $7, %xmm0
+; X64-NEXT:    retq
+  %a = call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> undef, i32 6)
+  store <4 x i32> %a, <4 x i32>* %dummy
+  %res = call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> undef, i32 7)
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @test18(<4 x i32> %a0, <4 x i32>* %dummy) {
+; X86-LABEL: test18:
+; X86:       # %bb.0:
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    pslld $3, %xmm0
+; X86-NEXT:    movdqa %xmm0, (%eax)
+; X86-NEXT:    pslld $1, %xmm0
+; X86-NEXT:    retl
+;
+; X64-LABEL: test18:
+; X64:       # %bb.0:
+; X64-NEXT:    pslld $3, %xmm0
+; X64-NEXT:    movdqa %xmm0, (%rdi)
+; X64-NEXT:    pslld $1, %xmm0
+; X64-NEXT:    retq
+  %a = call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> undef, i32 3)
+  store <4 x i32> %a, <4 x i32>* %dummy
+  %res = call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> undef, i32 1)
+  ret <4 x i32> %res
+}
+
 declare <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16>, i32)
 declare <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16>, i32)
 declare <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16>, i32)
-- 
2.7.4