From b57400a267c9f74d004219eddb8d5e48dd7472a6 Mon Sep 17 00:00:00 2001 From: William Qiu Date: Wed, 1 Mar 2023 16:45:11 +0800 Subject: [PATCH] riscv: dts: starfive: Add PWM node Adding StarFive PWM controller node to VisionFive 2 SoC. Signed-off-by: William Qiu --- .../dts/starfive/jh7110-starfive-visionfive-2.dtsi | 20 ++++++++++++++++++++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 9 +++++++++ 2 files changed, 29 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index 7684bf7..4633a2c 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -157,6 +157,12 @@ status = "okay"; }; +&ptc { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins>; + status = "okay"; +}; + &sysgpio { i2c0_pins: i2c0-0 { i2c-pins { @@ -214,6 +220,20 @@ }; }; + pwm_pins: pwm-0 { + pwm-pins { + pinmux = , + ; + bias-disable; + drive-strength = <12>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + }; + uart0_pins: uart0-0 { tx-pins { pinmux = ; + clocks = <&syscrg JH7110_SYSCLK_PWM_APB>; + resets = <&syscrg JH7110_SYSRST_PWM_APB>; + #pwm-cells=<3>; + status = "disabled"; + }; + qspi: spi@13010000 { compatible = "starfive,jh7110-qspi", "cdns,qspi-nor"; #address-cells = <1>; -- 2.7.4