From b56e6cd9b9bdd0fab494da1d0aa474b8c31c2a73 Mon Sep 17 00:00:00 2001 From: Colin LeMahieu Date: Mon, 8 Dec 2014 17:33:06 +0000 Subject: [PATCH] [Hexagon] Adding combine reg, reg with predicated forms. llvm-svn: 223667 --- llvm/lib/Target/Hexagon/HexagonInstrInfo.td | 7 +++++++ llvm/test/MC/Disassembler/Hexagon/alu32_perm.txt | 2 ++ llvm/test/MC/Disassembler/Hexagon/alu32_pred.txt | 4 ++++ 3 files changed, 13 insertions(+) diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td index 3158adc..99a02a9 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td @@ -208,6 +208,13 @@ def: BinOp32_pat; let OutOperandList = (outs DoubleRegs:$Rd), hasNewValue = 0, isCodeGenOnly = 0 in { def S2_packhl : T_ALU32_3op <"packhl", 0b101, 0b100, 0, 0>; + + let isPredicable = 1 in + def A2_combinew : T_ALU32_3op <"combine", 0b101, 0b000, 0, 0>; + + // Conditional combinew uses "newt/f" instead of "t/fnew". + def C2_ccombinewt : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 0, 0>; + def C2_ccombinewf : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 1, 0>; } let hasSideEffects = 0, hasNewValue = 1, isCompare = 1, InputType = "reg" in diff --git a/llvm/test/MC/Disassembler/Hexagon/alu32_perm.txt b/llvm/test/MC/Disassembler/Hexagon/alu32_perm.txt index 2f1d1b6..d895210 100644 --- a/llvm/test/MC/Disassembler/Hexagon/alu32_perm.txt +++ b/llvm/test/MC/Disassembler/Hexagon/alu32_perm.txt @@ -10,6 +10,8 @@ # CHECK: r17 = combine(r31.l, r21.l) 0xb0 0xe2 0x0f 0x7c # CHECK: r17:16 = combine(#21, #31) +0x10 0xdf 0x15 0xf5 +# CHECK: r17:16 = combine(r21, r31) 0xf1 0xc3 0x75 0x73 # CHECK: r17 = mux(p3, r21, #31) 0xb1 0xc2 0xff 0x73 diff --git a/llvm/test/MC/Disassembler/Hexagon/alu32_pred.txt b/llvm/test/MC/Disassembler/Hexagon/alu32_pred.txt index c85b86b..c17bd0f 100644 --- a/llvm/test/MC/Disassembler/Hexagon/alu32_pred.txt +++ b/llvm/test/MC/Disassembler/Hexagon/alu32_pred.txt @@ -6,6 +6,10 @@ # CHECK: if (p3) r17 = aslh(r21) 0x11 0xe3 0x35 0x70 # CHECK: if (p3) r17 = asrh(r21) +0x70 0xdf 0x15 0xfd +# CHECK: if (p3) r17:16 = combine(r21, r31) +0xf0 0xdf 0x15 0xfd +# CHECK: if (!p3) r17:16 = combine(r21, r31) 0x71 0xdf 0x15 0xf9 # CHECK: if (p3) r17 = and(r21, r31) 0x71 0xdf 0x35 0xf9 -- 2.7.4