From b56be79e0ca5bba43c64c4a9b5be1c750a340235 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Tue, 25 Sep 2018 13:01:26 +0000 Subject: [PATCH] Revert rL342916: [X86] Remove shift/rotate by CL memory (RMW) overrides As suggested by Craig Topper - I'm going to look at cleaning up the RMW sequences instead. The uops are slightly different to the register variant, so requires a +1uop tweak llvm-svn: 342969 --- llvm/lib/Target/X86/X86SchedBroadwell.td | 13 +++++--- llvm/lib/Target/X86/X86SchedHaswell.td | 13 +++++--- llvm/lib/Target/X86/X86SchedSandyBridge.td | 36 +++++++++++++++++----- llvm/lib/Target/X86/X86SchedSkylakeClient.td | 23 ++++++++++---- llvm/lib/Target/X86/X86SchedSkylakeServer.td | 23 ++++++++++---- llvm/test/CodeGen/X86/bmi2-schedule.ll | 16 +++++----- .../tools/llvm-mca/X86/Generic/resources-bmi2.s | 16 +++++----- 7 files changed, 97 insertions(+), 43 deletions(-) diff --git a/llvm/lib/Target/X86/X86SchedBroadwell.td b/llvm/lib/Target/X86/X86SchedBroadwell.td index bcaa0e2..a1624b0 100755 --- a/llvm/lib/Target/X86/X86SchedBroadwell.td +++ b/llvm/lib/Target/X86/X86SchedBroadwell.td @@ -84,7 +84,7 @@ def : ReadAdvance; multiclass BWWriteResPair ExePorts, int Lat, list Res = [1], int UOps = 1, - int LoadLat = 5, int LoadUOps = 1> { + int LoadLat = 5> { // Register variant is using a single cycle on ExePort. def : WriteRes { let Latency = Lat; @@ -97,7 +97,7 @@ multiclass BWWriteResPair { let Latency = !add(Lat, LoadLat); let ResourceCycles = !listconcat([1], Res); - let NumMicroOps = !add(UOps, LoadUOps); + let NumMicroOps = !add(UOps, 1); } } @@ -173,9 +173,9 @@ defm : BWWriteResPair; // Integer shifts and rotates. defm : BWWriteResPair; -defm : BWWriteResPair; +defm : BWWriteResPair; defm : BWWriteResPair; -defm : BWWriteResPair; +defm : BWWriteResPair; // SHLD/SHRD. defm : X86WriteRes; @@ -1167,6 +1167,11 @@ def BWWriteResGroup100 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPo let ResourceCycles = [1,1,1,2,1]; } def : SchedAlias; +def: InstRW<[BWWriteResGroup100], (instregex "ROL(8|16|32|64)mCL", + "ROR(8|16|32|64)mCL", + "SAR(8|16|32|64)mCL", + "SHL(8|16|32|64)mCL", + "SHR(8|16|32|64)mCL")>; def BWWriteResGroup101 : SchedWriteRes<[BWPort1,BWPort23]> { let Latency = 9; diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td index f409954..87f7919 100644 --- a/llvm/lib/Target/X86/X86SchedHaswell.td +++ b/llvm/lib/Target/X86/X86SchedHaswell.td @@ -89,7 +89,7 @@ def : ReadAdvance; multiclass HWWriteResPair ExePorts, int Lat, list Res = [1], int UOps = 1, - int LoadLat = 5, int LoadUOps = 1> { + int LoadLat = 5> { // Register variant is using a single cycle on ExePort. def : WriteRes { let Latency = Lat; @@ -102,7 +102,7 @@ multiclass HWWriteResPair { let Latency = !add(Lat, LoadLat); let ResourceCycles = !listconcat([1], Res); - let NumMicroOps = !add(UOps, LoadUOps); + let NumMicroOps = !add(UOps, 1); } } @@ -144,9 +144,9 @@ defm : X86WriteRes; // Integer shifts and rotates. defm : HWWriteResPair; -defm : HWWriteResPair; +defm : HWWriteResPair; defm : HWWriteResPair; -defm : HWWriteResPair; +defm : HWWriteResPair; // SHLD/SHRD. defm : X86WriteRes; @@ -1306,6 +1306,11 @@ def HWWriteResGroup69 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06,HWPor let NumMicroOps = 6; let ResourceCycles = [1,1,1,2,1]; } +def: InstRW<[HWWriteResGroup69], (instregex "ROL(8|16|32|64)mCL", + "ROR(8|16|32|64)mCL", + "SAR(8|16|32|64)mCL", + "SHL(8|16|32|64)mCL", + "SHR(8|16|32|64)mCL")>; def: SchedAlias; def HWWriteResGroup70 : SchedWriteRes<[HWPort0,HWPort1]> { diff --git a/llvm/lib/Target/X86/X86SchedSandyBridge.td b/llvm/lib/Target/X86/X86SchedSandyBridge.td index bfb283a..e01170a 100644 --- a/llvm/lib/Target/X86/X86SchedSandyBridge.td +++ b/llvm/lib/Target/X86/X86SchedSandyBridge.td @@ -79,7 +79,7 @@ def : ReadAdvance; multiclass SBWriteResPair ExePorts, int Lat, list Res = [1], int UOps = 1, - int LoadLat = 5, int LoadUOps = 1> { + int LoadLat = 5> { // Register variant is using a single cycle on ExePort. def : WriteRes { let Latency = Lat; @@ -92,7 +92,7 @@ multiclass SBWriteResPair { let Latency = !add(Lat, LoadLat); let ResourceCycles = !listconcat([1], Res); - let NumMicroOps = !add(UOps, LoadUOps); + let NumMicroOps = !add(UOps, 1); } } @@ -144,10 +144,10 @@ defm : X86WriteRes; defm : X86WriteRes; defm : X86WriteRes; -defm : SBWriteResPair; -defm : SBWriteResPair; -defm : SBWriteResPair; -defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; +defm : SBWriteResPair; defm : SBWriteResPair; defm : SBWriteResPair; @@ -924,7 +924,10 @@ def SBWriteResGroup69 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> { } def: InstRW<[SBWriteResGroup69], (instregex "BTC(16|32|64)mi8", "BTR(16|32|64)mi8", - "BTS(16|32|64)mi8")>; + "BTS(16|32|64)mi8", + "SAR(8|16|32|64)m(1|i)", + "SHL(8|16|32|64)m(1|i)", + "SHR(8|16|32|64)m(1|i)")>; def SBWriteResGroup77 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> { let Latency = 8; @@ -957,6 +960,14 @@ def SBWriteResGroup84 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> { } def: InstRW<[SBWriteResGroup84], (instrs FLDCW16m)>; +def SBWriteResGroup85 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> { + let Latency = 8; + let NumMicroOps = 5; + let ResourceCycles = [1,2,2]; +} +def: InstRW<[SBWriteResGroup85], (instregex "ROL(8|16|32|64)m(1|i)", + "ROR(8|16|32|64)m(1|i)")>; + def SBWriteResGroup86 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> { let Latency = 8; let NumMicroOps = 5; @@ -994,6 +1005,17 @@ def SBWriteResGroup97 : SchedWriteRes<[SBPort1,SBPort4,SBPort23]> { def: InstRW<[SBWriteResGroup97], (instregex "IST_F(16|32)m", "IST_FP(16|32|64)m")>; +def SBWriteResGroup97_2 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> { + let Latency = 9; + let NumMicroOps = 6; + let ResourceCycles = [1,2,3]; +} +def: InstRW<[SBWriteResGroup97_2], (instregex "ROL(8|16|32|64)mCL", + "ROR(8|16|32|64)mCL", + "SAR(8|16|32|64)mCL", + "SHL(8|16|32|64)mCL", + "SHR(8|16|32|64)mCL")>; + def SBWriteResGroup98 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> { let Latency = 9; let NumMicroOps = 6; diff --git a/llvm/lib/Target/X86/X86SchedSkylakeClient.td b/llvm/lib/Target/X86/X86SchedSkylakeClient.td index b993a11..b0fc3a2 100644 --- a/llvm/lib/Target/X86/X86SchedSkylakeClient.td +++ b/llvm/lib/Target/X86/X86SchedSkylakeClient.td @@ -83,7 +83,7 @@ def : ReadAdvance; multiclass SKLWriteResPair ExePorts, int Lat, list Res = [1], int UOps = 1, - int LoadLat = 5, int LoadUOps = 1> { + int LoadLat = 5> { // Register variant is using a single cycle on ExePort. def : WriteRes { let Latency = Lat; @@ -96,7 +96,7 @@ multiclass SKLWriteResPair { let Latency = !add(Lat, LoadLat); let ResourceCycles = !listconcat([1], Res); - let NumMicroOps = !add(UOps, LoadUOps); + let NumMicroOps = !add(UOps, 1); } } @@ -169,10 +169,10 @@ defm : SKLWriteResPair; defm : SKLWriteResPair; // Integer shifts and rotates. -defm : SKLWriteResPair; -defm : SKLWriteResPair; -defm : SKLWriteResPair; -defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : SKLWriteResPair; +defm : SKLWriteResPair; // SHLD/SHRD. defm : X86WriteRes; @@ -1246,6 +1246,17 @@ def SKLWriteResGroup116 : SchedWriteRes<[SKLPort23,SKLPort237,SKLPort06,SKLPort0 def: InstRW<[SKLWriteResGroup116], (instregex "RCL(8|16|32|64)m(1|i)", "RCR(8|16|32|64)m(1|i)")>; +def SKLWriteResGroup117 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> { + let Latency = 8; + let NumMicroOps = 6; + let ResourceCycles = [1,1,1,3]; +} +def: InstRW<[SKLWriteResGroup117], (instregex "ROL(8|16|32|64)mCL", + "ROR(8|16|32|64)mCL", + "SAR(8|16|32|64)mCL", + "SHL(8|16|32|64)mCL", + "SHR(8|16|32|64)mCL")>; + def SKLWriteResGroup119 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> { let Latency = 8; let NumMicroOps = 6; diff --git a/llvm/lib/Target/X86/X86SchedSkylakeServer.td b/llvm/lib/Target/X86/X86SchedSkylakeServer.td index 72f3765e..d34d790 100755 --- a/llvm/lib/Target/X86/X86SchedSkylakeServer.td +++ b/llvm/lib/Target/X86/X86SchedSkylakeServer.td @@ -83,7 +83,7 @@ def : ReadAdvance; multiclass SKXWriteResPair ExePorts, int Lat, list Res = [1], int UOps = 1, - int LoadLat = 5, int LoadUOps = 1> { + int LoadLat = 5> { // Register variant is using a single cycle on ExePort. def : WriteRes { let Latency = Lat; @@ -96,7 +96,7 @@ multiclass SKXWriteResPair { let Latency = !add(Lat, LoadLat); let ResourceCycles = !listconcat([1], Res); - let NumMicroOps = !add(UOps, LoadUOps); + let NumMicroOps = !add(UOps, 1); } } @@ -163,10 +163,10 @@ def : WriteRes; def : WriteRes; // // Integer shifts and rotates. -defm : SKXWriteResPair; -defm : SKXWriteResPair; -defm : SKXWriteResPair; -defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; // SHLD/SHRD. defm : X86WriteRes; @@ -1599,6 +1599,17 @@ def SKXWriteResGroup127 : SchedWriteRes<[SKXPort23,SKXPort237,SKXPort06,SKXPort0 def: InstRW<[SKXWriteResGroup127], (instregex "RCL(8|16|32|64)m(1|i)", "RCR(8|16|32|64)m(1|i)")>; +def SKXWriteResGroup128 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]> { + let Latency = 8; + let NumMicroOps = 6; + let ResourceCycles = [1,1,1,3]; +} +def: InstRW<[SKXWriteResGroup128], (instregex "ROL(8|16|32|64)mCL", + "ROR(8|16|32|64)mCL", + "SAR(8|16|32|64)mCL", + "SHL(8|16|32|64)mCL", + "SHR(8|16|32|64)mCL")>; + def SKXWriteResGroup130 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> { let Latency = 8; let NumMicroOps = 6; diff --git a/llvm/test/CodeGen/X86/bmi2-schedule.ll b/llvm/test/CodeGen/X86/bmi2-schedule.ll index 37fb2b2..5232e51 100644 --- a/llvm/test/CodeGen/X86/bmi2-schedule.ll +++ b/llvm/test/CodeGen/X86/bmi2-schedule.ll @@ -430,7 +430,7 @@ define i32 @test_rorx_i32(i32 %a0, i32 %a1, i32 *%a2) { ; GENERIC-LABEL: test_rorx_i32: ; GENERIC: # %bb.0: ; GENERIC-NEXT: rorxl $5, %edi, %ecx # sched: [1:0.50] -; GENERIC-NEXT: rorxl $5, (%rdx), %eax # sched: [7:0.50] +; GENERIC-NEXT: rorxl $5, (%rdx), %eax # sched: [6:0.50] ; GENERIC-NEXT: addl %ecx, %eax # sched: [1:0.33] ; GENERIC-NEXT: retq # sched: [1:1.00] ; @@ -483,7 +483,7 @@ define i64 @test_rorx_i64(i64 %a0, i64 %a1, i64 *%a2) { ; GENERIC-LABEL: test_rorx_i64: ; GENERIC: # %bb.0: ; GENERIC-NEXT: rorxq $5, %rdi, %rcx # sched: [1:0.50] -; GENERIC-NEXT: rorxq $5, (%rdx), %rax # sched: [7:0.50] +; GENERIC-NEXT: rorxq $5, (%rdx), %rax # sched: [6:0.50] ; GENERIC-NEXT: addq %rcx, %rax # sched: [1:0.33] ; GENERIC-NEXT: retq # sched: [1:1.00] ; @@ -536,7 +536,7 @@ define i32 @test_sarx_i32(i32 %a0, i32 %a1, i32 *%a2) { ; GENERIC-LABEL: test_sarx_i32: ; GENERIC: # %bb.0: ; GENERIC-NEXT: sarxl %esi, %edi, %ecx # sched: [1:0.50] -; GENERIC-NEXT: sarxl %esi, (%rdx), %eax # sched: [7:0.50] +; GENERIC-NEXT: sarxl %esi, (%rdx), %eax # sched: [6:0.50] ; GENERIC-NEXT: addl %ecx, %eax # sched: [1:0.33] ; GENERIC-NEXT: retq # sched: [1:1.00] ; @@ -585,7 +585,7 @@ define i64 @test_sarx_i64(i64 %a0, i64 %a1, i64 *%a2) { ; GENERIC-LABEL: test_sarx_i64: ; GENERIC: # %bb.0: ; GENERIC-NEXT: sarxq %rsi, %rdi, %rcx # sched: [1:0.50] -; GENERIC-NEXT: sarxq %rsi, (%rdx), %rax # sched: [7:0.50] +; GENERIC-NEXT: sarxq %rsi, (%rdx), %rax # sched: [6:0.50] ; GENERIC-NEXT: addq %rcx, %rax # sched: [1:0.33] ; GENERIC-NEXT: retq # sched: [1:1.00] ; @@ -634,7 +634,7 @@ define i32 @test_shlx_i32(i32 %a0, i32 %a1, i32 *%a2) { ; GENERIC-LABEL: test_shlx_i32: ; GENERIC: # %bb.0: ; GENERIC-NEXT: shlxl %esi, %edi, %ecx # sched: [1:0.50] -; GENERIC-NEXT: shlxl %esi, (%rdx), %eax # sched: [7:0.50] +; GENERIC-NEXT: shlxl %esi, (%rdx), %eax # sched: [6:0.50] ; GENERIC-NEXT: addl %ecx, %eax # sched: [1:0.33] ; GENERIC-NEXT: retq # sched: [1:1.00] ; @@ -683,7 +683,7 @@ define i64 @test_shlx_i64(i64 %a0, i64 %a1, i64 *%a2) { ; GENERIC-LABEL: test_shlx_i64: ; GENERIC: # %bb.0: ; GENERIC-NEXT: shlxq %rsi, %rdi, %rcx # sched: [1:0.50] -; GENERIC-NEXT: shlxq %rsi, (%rdx), %rax # sched: [7:0.50] +; GENERIC-NEXT: shlxq %rsi, (%rdx), %rax # sched: [6:0.50] ; GENERIC-NEXT: addq %rcx, %rax # sched: [1:0.33] ; GENERIC-NEXT: retq # sched: [1:1.00] ; @@ -732,7 +732,7 @@ define i32 @test_shrx_i32(i32 %a0, i32 %a1, i32 *%a2) { ; GENERIC-LABEL: test_shrx_i32: ; GENERIC: # %bb.0: ; GENERIC-NEXT: shrxl %esi, %edi, %ecx # sched: [1:0.50] -; GENERIC-NEXT: shrxl %esi, (%rdx), %eax # sched: [7:0.50] +; GENERIC-NEXT: shrxl %esi, (%rdx), %eax # sched: [6:0.50] ; GENERIC-NEXT: addl %ecx, %eax # sched: [1:0.33] ; GENERIC-NEXT: retq # sched: [1:1.00] ; @@ -781,7 +781,7 @@ define i64 @test_shrx_i64(i64 %a0, i64 %a1, i64 *%a2) { ; GENERIC-LABEL: test_shrx_i64: ; GENERIC: # %bb.0: ; GENERIC-NEXT: shrxq %rsi, %rdi, %rcx # sched: [1:0.50] -; GENERIC-NEXT: shrxq %rsi, (%rdx), %rax # sched: [7:0.50] +; GENERIC-NEXT: shrxq %rsi, (%rdx), %rax # sched: [6:0.50] ; GENERIC-NEXT: addq %rcx, %rax # sched: [1:0.33] ; GENERIC-NEXT: retq # sched: [1:1.00] ; diff --git a/llvm/test/tools/llvm-mca/X86/Generic/resources-bmi2.s b/llvm/test/tools/llvm-mca/X86/Generic/resources-bmi2.s index 36217e8..6c7382a 100644 --- a/llvm/test/tools/llvm-mca/X86/Generic/resources-bmi2.s +++ b/llvm/test/tools/llvm-mca/X86/Generic/resources-bmi2.s @@ -75,21 +75,21 @@ shrx %rax, (%rbx), %rcx # CHECK-NEXT: 1 1 0.33 pextq %rax, %rbx, %rcx # CHECK-NEXT: 2 6 0.50 * pextq (%rax), %rbx, %rcx # CHECK-NEXT: 1 1 0.50 rorxl $1, %eax, %ecx -# CHECK-NEXT: 3 7 0.50 * rorxl $1, (%rax), %ecx +# CHECK-NEXT: 2 6 0.50 * rorxl $1, (%rax), %ecx # CHECK-NEXT: 1 1 0.50 rorxq $1, %rax, %rcx -# CHECK-NEXT: 3 7 0.50 * rorxq $1, (%rax), %rcx +# CHECK-NEXT: 2 6 0.50 * rorxq $1, (%rax), %rcx # CHECK-NEXT: 1 1 0.50 sarxl %eax, %ebx, %ecx -# CHECK-NEXT: 3 7 0.50 * sarxl %eax, (%rbx), %ecx +# CHECK-NEXT: 2 6 0.50 * sarxl %eax, (%rbx), %ecx # CHECK-NEXT: 1 1 0.50 sarxq %rax, %rbx, %rcx -# CHECK-NEXT: 3 7 0.50 * sarxq %rax, (%rbx), %rcx +# CHECK-NEXT: 2 6 0.50 * sarxq %rax, (%rbx), %rcx # CHECK-NEXT: 1 1 0.50 shlxl %eax, %ebx, %ecx -# CHECK-NEXT: 3 7 0.50 * shlxl %eax, (%rbx), %ecx +# CHECK-NEXT: 2 6 0.50 * shlxl %eax, (%rbx), %ecx # CHECK-NEXT: 1 1 0.50 shlxq %rax, %rbx, %rcx -# CHECK-NEXT: 3 7 0.50 * shlxq %rax, (%rbx), %rcx +# CHECK-NEXT: 2 6 0.50 * shlxq %rax, (%rbx), %rcx # CHECK-NEXT: 1 1 0.50 shrxl %eax, %ebx, %ecx -# CHECK-NEXT: 3 7 0.50 * shrxl %eax, (%rbx), %ecx +# CHECK-NEXT: 2 6 0.50 * shrxl %eax, (%rbx), %ecx # CHECK-NEXT: 1 1 0.50 shrxq %rax, %rbx, %rcx -# CHECK-NEXT: 3 7 0.50 * shrxq %rax, (%rbx), %rcx +# CHECK-NEXT: 2 6 0.50 * shrxq %rax, (%rbx), %rcx # CHECK: Resources: # CHECK-NEXT: [0] - SBDivider -- 2.7.4