From b4c49255aa8f9ec119ee940a94854f9225ae89e4 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 18 Mar 2019 05:48:18 +0000 Subject: [PATCH] [X86] Make ADD*_DB post-RA pseudos and expand them in expandPostRAPseudo. These are used to help convert OR->LEA when needed to avoid avoid a copy. They aren't need after register allocation. Happens to remove an ugly goto from X86MCCodeEmitter.cpp llvm-svn: 356356 --- llvm/lib/Target/X86/X86InstrCompiler.td | 2 +- llvm/lib/Target/X86/X86InstrFoldTables.cpp | 30 +++++++++++++++--------------- llvm/lib/Target/X86/X86InstrInfo.cpp | 11 +++++++++++ llvm/lib/Target/X86/X86MCInstLower.cpp | 16 ---------------- 4 files changed, 27 insertions(+), 32 deletions(-) diff --git a/llvm/lib/Target/X86/X86InstrCompiler.td b/llvm/lib/Target/X86/X86InstrCompiler.td index e4f324e..44f2ac4 100644 --- a/llvm/lib/Target/X86/X86InstrCompiler.td +++ b/llvm/lib/Target/X86/X86InstrCompiler.td @@ -1378,7 +1378,7 @@ def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{ // Try this before the selecting to OR. let SchedRW = [WriteALU] in { -let isConvertibleToThreeAddress = 1, +let isConvertibleToThreeAddress = 1, isPseudo = 1, Constraints = "$src1 = $dst", Defs = [EFLAGS] in { let isCommutable = 1 in { def ADD8rr_DB : I<0, Pseudo, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2), diff --git a/llvm/lib/Target/X86/X86InstrFoldTables.cpp b/llvm/lib/Target/X86/X86InstrFoldTables.cpp index 5cd327f..d8c21f6 100644 --- a/llvm/lib/Target/X86/X86InstrFoldTables.cpp +++ b/llvm/lib/Target/X86/X86InstrFoldTables.cpp @@ -33,6 +33,17 @@ using namespace llvm; // tables that would be incorrect. The manual review process allows us a chance // to catch these before they become observable bugs. static const X86MemoryFoldTableEntry MemoryFoldTable2Addr[] = { + { X86::ADD16ri8_DB, X86::ADD16mi8, TB_NO_REVERSE }, + { X86::ADD16ri_DB, X86::ADD16mi, TB_NO_REVERSE }, + { X86::ADD16rr_DB, X86::ADD16mr, TB_NO_REVERSE }, + { X86::ADD32ri8_DB, X86::ADD32mi8, TB_NO_REVERSE }, + { X86::ADD32ri_DB, X86::ADD32mi, TB_NO_REVERSE }, + { X86::ADD32rr_DB, X86::ADD32mr, TB_NO_REVERSE }, + { X86::ADD64ri32_DB,X86::ADD64mi32, TB_NO_REVERSE }, + { X86::ADD64ri8_DB, X86::ADD64mi8, TB_NO_REVERSE }, + { X86::ADD64rr_DB, X86::ADD64mr, TB_NO_REVERSE }, + { X86::ADD8ri_DB, X86::ADD8mi, TB_NO_REVERSE }, + { X86::ADD8rr_DB, X86::ADD8mr, TB_NO_REVERSE }, { X86::ADC16ri, X86::ADC16mi, 0 }, { X86::ADC16ri8, X86::ADC16mi8, 0 }, { X86::ADC16rr, X86::ADC16mr, 0 }, @@ -47,27 +58,16 @@ static const X86MemoryFoldTableEntry MemoryFoldTable2Addr[] = { { X86::ADC8rr, X86::ADC8mr, 0 }, { X86::ADD16ri, X86::ADD16mi, 0 }, { X86::ADD16ri8, X86::ADD16mi8, 0 }, - { X86::ADD16ri8_DB, X86::ADD16mi8, TB_NO_REVERSE }, - { X86::ADD16ri_DB, X86::ADD16mi, TB_NO_REVERSE }, { X86::ADD16rr, X86::ADD16mr, 0 }, - { X86::ADD16rr_DB, X86::ADD16mr, TB_NO_REVERSE }, { X86::ADD32ri, X86::ADD32mi, 0 }, { X86::ADD32ri8, X86::ADD32mi8, 0 }, - { X86::ADD32ri8_DB, X86::ADD32mi8, TB_NO_REVERSE }, - { X86::ADD32ri_DB, X86::ADD32mi, TB_NO_REVERSE }, { X86::ADD32rr, X86::ADD32mr, 0 }, - { X86::ADD32rr_DB, X86::ADD32mr, TB_NO_REVERSE }, { X86::ADD64ri32, X86::ADD64mi32, 0 }, - { X86::ADD64ri32_DB,X86::ADD64mi32, TB_NO_REVERSE }, { X86::ADD64ri8, X86::ADD64mi8, 0 }, - { X86::ADD64ri8_DB, X86::ADD64mi8, TB_NO_REVERSE }, { X86::ADD64rr, X86::ADD64mr, 0 }, - { X86::ADD64rr_DB, X86::ADD64mr, TB_NO_REVERSE }, { X86::ADD8ri, X86::ADD8mi, 0 }, { X86::ADD8ri8, X86::ADD8mi8, 0 }, - { X86::ADD8ri_DB, X86::ADD8mi, TB_NO_REVERSE }, { X86::ADD8rr, X86::ADD8mr, 0 }, - { X86::ADD8rr_DB, X86::ADD8mr, TB_NO_REVERSE }, { X86::AND16ri, X86::AND16mi, 0 }, { X86::AND16ri8, X86::AND16mi8, 0 }, { X86::AND16rr, X86::AND16mr, 0 }, @@ -1207,6 +1207,10 @@ static const X86MemoryFoldTableEntry MemoryFoldTable1[] = { }; static const X86MemoryFoldTableEntry MemoryFoldTable2[] = { + { X86::ADD16rr_DB, X86::ADD16rm, TB_NO_REVERSE }, + { X86::ADD32rr_DB, X86::ADD32rm, TB_NO_REVERSE }, + { X86::ADD64rr_DB, X86::ADD64rm, TB_NO_REVERSE }, + { X86::ADD8rr_DB, X86::ADD8rm, TB_NO_REVERSE }, { X86::ADC16rr, X86::ADC16rm, 0 }, { X86::ADC32rr, X86::ADC32rm, 0 }, { X86::ADC64rr, X86::ADC64rm, 0 }, @@ -1214,13 +1218,9 @@ static const X86MemoryFoldTableEntry MemoryFoldTable2[] = { { X86::ADCX32rr, X86::ADCX32rm, 0 }, { X86::ADCX64rr, X86::ADCX64rm, 0 }, { X86::ADD16rr, X86::ADD16rm, 0 }, - { X86::ADD16rr_DB, X86::ADD16rm, TB_NO_REVERSE }, { X86::ADD32rr, X86::ADD32rm, 0 }, - { X86::ADD32rr_DB, X86::ADD32rm, TB_NO_REVERSE }, { X86::ADD64rr, X86::ADD64rm, 0 }, - { X86::ADD64rr_DB, X86::ADD64rm, TB_NO_REVERSE }, { X86::ADD8rr, X86::ADD8rm, 0 }, - { X86::ADD8rr_DB, X86::ADD8rm, TB_NO_REVERSE }, { X86::ADDPDrr, X86::ADDPDrm, TB_ALIGN_16 }, { X86::ADDPSrr, X86::ADDPSrm, TB_ALIGN_16 }, { X86::ADDSDrr, X86::ADDSDrm, 0 }, diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index 21db322..c03b602 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -4237,6 +4237,17 @@ bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const { case X86::XOR64_FP: case X86::XOR32_FP: return expandXorFP(MIB, *this); + case X86::ADD8rr_DB: MIB->setDesc(get(X86::OR8rr)); break; + case X86::ADD16rr_DB: MIB->setDesc(get(X86::OR16rr)); break; + case X86::ADD32rr_DB: MIB->setDesc(get(X86::OR32rr)); break; + case X86::ADD64rr_DB: MIB->setDesc(get(X86::OR64rr)); break; + case X86::ADD8ri_DB: MIB->setDesc(get(X86::OR8ri)); break; + case X86::ADD16ri_DB: MIB->setDesc(get(X86::OR16ri)); break; + case X86::ADD32ri_DB: MIB->setDesc(get(X86::OR32ri)); break; + case X86::ADD64ri32_DB: MIB->setDesc(get(X86::OR64ri32)); break; + case X86::ADD16ri8_DB: MIB->setDesc(get(X86::OR16ri8)); break; + case X86::ADD32ri8_DB: MIB->setDesc(get(X86::OR32ri8)); break; + case X86::ADD64ri8_DB: MIB->setDesc(get(X86::OR64ri8)); break; } return false; } diff --git a/llvm/lib/Target/X86/X86MCInstLower.cpp b/llvm/lib/Target/X86/X86MCInstLower.cpp index 4b62085..cd1dcf3 100644 --- a/llvm/lib/Target/X86/X86MCInstLower.cpp +++ b/llvm/lib/Target/X86/X86MCInstLower.cpp @@ -435,7 +435,6 @@ void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { OutMI.addOperand(MaybeMCOp.getValue()); // Handle a few special cases to eliminate operand modifiers. -ReSimplify: switch (OutMI.getOpcode()) { case X86::LEA64_32r: case X86::LEA64r: @@ -583,21 +582,6 @@ ReSimplify: } break; - // These are pseudo-ops for OR to help with the OR->ADD transformation. We do - // this with an ugly goto in case the resultant OR uses EAX and needs the - // short form. - case X86::ADD8rr_DB: OutMI.setOpcode(X86::OR8rr); goto ReSimplify; - case X86::ADD16rr_DB: OutMI.setOpcode(X86::OR16rr); goto ReSimplify; - case X86::ADD32rr_DB: OutMI.setOpcode(X86::OR32rr); goto ReSimplify; - case X86::ADD64rr_DB: OutMI.setOpcode(X86::OR64rr); goto ReSimplify; - case X86::ADD8ri_DB: OutMI.setOpcode(X86::OR8ri); goto ReSimplify; - case X86::ADD16ri_DB: OutMI.setOpcode(X86::OR16ri); goto ReSimplify; - case X86::ADD32ri_DB: OutMI.setOpcode(X86::OR32ri); goto ReSimplify; - case X86::ADD64ri32_DB: OutMI.setOpcode(X86::OR64ri32); goto ReSimplify; - case X86::ADD16ri8_DB: OutMI.setOpcode(X86::OR16ri8); goto ReSimplify; - case X86::ADD32ri8_DB: OutMI.setOpcode(X86::OR32ri8); goto ReSimplify; - case X86::ADD64ri8_DB: OutMI.setOpcode(X86::OR64ri8); goto ReSimplify; - // We don't currently select the correct instruction form for instructions // which have a short %eax, etc. form. Handle this by custom lowering, for // now. -- 2.7.4