From b4c032178c219db4c005a59c96c565e1f7dca7eb Mon Sep 17 00:00:00 2001 From: yicheng shen Date: Mon, 8 Apr 2019 23:45:19 -0400 Subject: [PATCH] hdmirx: optimize phy setting [1/1] PD#SWPL-3463 Problem: Need update phy setting Solution: 1.decrease pll bw; 2.add cdr lock level option 3.optimize signal detection time Verify: TL1 Change-Id: Idc24683430488d300fa2690fa9f8039905cf6a88 Signed-off-by: yicheng shen --- .../amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.h | 2 +- drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c | 147 ++++++++------------- drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.h | 1 + .../media/vin/tvin/hdmirx/hdmi_rx_wrapper.c | 58 +++++++- 4 files changed, 112 insertions(+), 96 deletions(-) diff --git a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.h b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.h index 161dfe8..6bf1d77 100644 --- a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.h +++ b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.h @@ -34,7 +34,7 @@ #include "hdmi_rx_edid.h" -#define RX_VER0 "ver.2019-04-02" +#define RX_VER0 "ver.2019-04-09" /* * * diff --git a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c index de8a22c..f011828 100644 --- a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c +++ b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c @@ -97,6 +97,8 @@ int ignore_sscp_tmds = 1; int find_best_eq; int eq_try_cnt = 20; int pll_rst_max; +/* cd lock threshold */ +int cdr_lock_level; /*------------------------variable define end------------------------------*/ static int check_regmap_flag(unsigned int addr) @@ -3367,70 +3369,68 @@ uint32_t aml_phy_pll_band(uint32_t cableclk, } static const uint32_t phy_misci[][4] = { - /* 0xd7 0xd8 0xe0 0xe1 */ + /* 0xd7 0xd8 0xe0 0xe1 */ { /* 24~45M */ - 0x3003707f, 0x00000080, 0x02218000, 0x00000010, + 0x3003707f, 0x00000080, 0x02218000, 0x00000010, }, { /* 45~74.5M */ - 0x3003707f, 0x00000080, 0x02218000, 0x00000010, + 0x3003707f, 0x00000080, 0x02218000, 0x00000010, }, { /* 77~155M */ - 0x3003707f, 0x00000080, 0x02218000, 0x00000010, + 0x3003707f, 0x00000080, 0x02218000, 0x00000010, }, { /* 155~340M */ - 0x3003707f, 0x00000080, 0x02218000, 0x00000010, + 0x3003707f, 0x00000080, 0x02218000, 0x00000010, }, { /* 340~525M */ - 0x3003707f, 0x007f0080, 0x02218000, 0x00000010, + 0x3003707f, 0x007f0080, 0x02218000, 0x00000010, }, { /* 525~600M */ - /* 0x3003707f, 0x007f0080, 0x02218000, 0x00000010, */ - 0x30037079, 0x007f8080, 0x02218000, 0x00000010, + 0x3003707f, 0x007f8080, 0x02218000, 0x00000010, }, }; static const uint32_t phy_dcha[][3] = { - /* 0xe2 0xe3 0xe4 */ + /* 0xe2 0xe3 0xe4 */ { /* 24~45M */ - 0x00000280, 0x4400c202, 0x030088a2, + 0x00000280, 0x4400c202, 0x030088a2, }, { /* 45~74.5M */ 0x00000280, 0x4400c202, 0x030088a2, }, { /* 77~155M */ - 0x000002a2, 0x6800c202, 0x01009126, + 0x000002a2, 0x6800c202, 0x01009126, }, { /* 155~340M */ - 0x000002a2, 0x0800c202, 0x0100cc31, + 0x00000280, 0x0800c202, 0x0100cc31, }, { /* 340~525M */ - 0x000002a2, 0x0700003c, 0x1d00cc31, + 0x00000280, 0x0700003c, 0x1d00cc31, }, { /* 525~600M */ - /* 0x000002a2, 0x0700003c, 0x1d00cc31, */ - 0x00000282, 0x07000000, 0x1d00cc31, + 0x00000280, 0x07000000, 0x1d00cc31, }, }; static const uint32_t phy_dcha_reva[][3] = { - /* 0xe2 0xe3 0xe4 */ + /* 0xe2 0xe3 0xe4 */ { /* 24~45M */ - 0x00000280, 0x2400c202, 0x030088a2, + 0x00000280, 0x2400c202, 0x030088a2, }, { /* 45~74.5M */ 0x00000280, 0x2400c202, 0x030088a2, }, { /* 77~155M */ - 0x000002a2, 0x4800c202, 0x01009126, + 0x000002a2, 0x4800c202, 0x01009126, }, { /* 155~340M */ - 0x000002a2, 0x0800c202, 0x0100cc31, + 0x000002a2, 0x0800c202, 0x0100cc31, }, { /* 340~525M */ - 0x000002a2, 0x0700003c, 0x1d00cc31, + 0x000002a2, 0x0700003c, 0x1d00cc31, }, { /* 525~600M */ - 0x000002a2, 0x0700003c, 0x1d00cc31, + 0x000002a2, 0x0700003c, 0x1d00cc31, }, }; @@ -3448,85 +3448,36 @@ static const uint32_t phy_dchd_1[][3] = { 0x003c714a, 0x1e062620, 0x00018000, }, { /* 155~340M */ - 0x003c714a, 0x1e062620, 0x00018000, + 0x003c714a, 0x1e050064, 0x0001a000, }, { /* 340~525M */ - 0x003c714a, 0x1e051650, 0x0001a000, + 0x003c714a, 0x1e050064, 0x0001a000, }, { /* 525~600M */ - /*0x002c714a, 0x1e051650, 0x00018000,*/ - 0x003e714a, 0x1e050560, 0x0001a000, + 0x003e714a, 0x1e050560, 0x0001a000, }, }; /* short cable */ static const uint32_t phy_dchd_2[][3] = { - /* 0xe5 0xe6 0xe7 */ + /* 0xe5 0xe6 0xe7 */ { /* 24~45M */ - 0x003e714a, 0x1e022220, 0x00018000, - }, - { /* 45~74.5M */ 0x003e714a, 0x1e022220, 0x00018000, }, - { /* 77~155M */ - 0x003c714a, 0x1e022220, 0x00018000, - }, - { /* 155~340M */ - 0x003c714a, 0x1e022220, 0x00018000, - }, - { /* 340~525M */ - 0x003c714a, 0x1e022220, 0x0001a000, - }, - { /* 525~600M */ - /*0x002c714a, 0x1e022220, 0x00018000,*/ - 0x003e714a, 0x1e022220, 0x0001a000, - }, -}; - - -/* long cable */ -static const uint32_t phy_dchd_3[][3] = { - /* 0xe5 0xe6 0xe7 */ - { /* 24~45M */ - 0x002e712a, 0x1e062620, 0x00018000, - }, { /* 45~74.5M */ - 0x002e714a, 0x1e062620, 0x00018000, - }, - { /* 77~155M */ - 0x002c715a, 0x1e062620, 0x00018000, - }, - { /* 155~340M */ - 0x002c715a, 0x1e062620, 0x00018000, - }, - { /* 340~525M */ - 0x002c715a, 0x1e051650, 0x00018000, - }, - { /* 525~600M */ - 0x002c715a, 0x1e051650, 0x00018000, - }, -}; - -/* short cable */ -static const uint32_t phy_dchd_4[][3] = { - /* 0xe5 0xe6 0xe7 */ - { /* 24~45M */ - 0x002e712a, 0x1e022220, 0x00018000, - }, - { /* 45~74.5M */ - 0x002e714a, 0x1e022220, 0x00018000, + 0x003e714a, 0x1e022220, 0x00018000, }, { /* 77~155M */ - 0x002c715a, 0x1e022220, 0x00018000, + 0x003c714a, 0x1e022220, 0x00018000, }, { /* 155~340M */ - 0x002c715a, 0x1e022220, 0x00018000, + 0x003c714a, 0x1e022220, 0x0001a000, }, { /* 340~525M */ - 0x002c715a, 0x1e012330, 0x0001a000, + 0x003c714a, 0x1e040460, 0x0001a000, }, { /* 525~600M */ - 0x002c715a, 0x1e022220, 0x00018000, + 0x003e714a, 0x1e040460, 0x0001a000, }, }; @@ -3587,8 +3538,15 @@ void aml_phy_init_1(void) wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL2, phy_dcha[idx][2]); } - wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL0, - phy_dchd_1[idx][0]); + if (cdr_lock_level == 0) + wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL0, + phy_dchd_1[idx][0]); + else if (cdr_lock_level == 1) + wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL0, + 0x006f0041); + else if (cdr_lock_level == 2) + wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL0, + 0x002f714a); wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL2, phy_dchd_1[idx][2]); @@ -3669,7 +3627,18 @@ void aml_phy_init(void) phy_dcha[idx][2]); } - wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL0, phy_dchd_1[idx][0]); + if (cdr_lock_level == 0) + wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL0, + phy_dchd_1[idx][0]); + else if (cdr_lock_level == 1) + wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL0, + 0x006f0041); + else if (cdr_lock_level == 2) + wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL0, + 0x002f714a); + wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL2, + phy_dchd_1[idx][2]); + wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL2, phy_dchd_1[idx][2]); if ((rx.phy.cablesel % 2) == 0) data32 = phy_dchd_1[idx][1]; @@ -3690,18 +3659,11 @@ void aml_eq_setting(void) if (find_best_eq) { data32 = phy_dchd_1[idx][1] & (~(MSK(16, 4))); data32 |= find_best_eq << 4; - } else if ((rx.phy.cablesel % 4) == 0) + } else if ((rx.phy.cablesel % 2) == 0) data32 = phy_dchd_1[idx][1]; - - else if ((rx.phy.cablesel % 4) == 1) + else if ((rx.phy.cablesel % 2) == 1) data32 = phy_dchd_2[idx][1]; - else if ((rx.phy.cablesel % 4) == 2) - data32 = phy_dchd_3[idx][1]; - - else if ((rx.phy.cablesel % 4) == 3) - data32 = phy_dchd_4[idx][1]; - wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, data32); udelay(5); @@ -3869,7 +3831,8 @@ void aml_phy_pll_setting(void) if (is_tl1_former()) data2 = 0x000100c0; else - data2 = 0x080100c0; + /* decrease pll bw*/ + data2 = 0x080130c0;//0x080100c0 data2 |= (od << 24); wr_reg_hhi(HHI_HDMIRX_APLL_CNTL4, data2); udelay(5); diff --git a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.h b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.h index 4b1e000..65a8c50 100644 --- a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.h +++ b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.h @@ -1113,6 +1113,7 @@ extern int ignore_sscp_tmds; extern int find_best_eq; extern int eq_try_cnt; extern int pll_rst_max; +extern int cdr_lock_level; extern void rx_get_best_eq_setting(void); extern int hbr_force_8ch; extern void wr_reg_hhi(unsigned int offset, unsigned int val); diff --git a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_wrapper.c b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_wrapper.c index 4e1705a..578577b 100644 --- a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_wrapper.c +++ b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_wrapper.c @@ -69,7 +69,7 @@ static int hpd_wait_cnt; static int hpd_wait_max = 40; static int sig_unstable_cnt; -static int sig_unstable_max = 80; +static int sig_unstable_max = 40;/* 80 */ bool vic_check_en; bool dvi_check_en; @@ -203,7 +203,7 @@ static bool hdcp22_stop_auth_enable; static bool hdcp22_esm_reset2_enable; int sm_pause; int pre_port = 0xff; -static int hdcp_none_wait_max = 100; +static int hdcp_none_wait_max = 50;/* 100 */ static int esd_phy_rst_cnt; static int esd_phy_rst_max; static int cec_dev_info; @@ -1716,6 +1716,8 @@ int rx_set_global_variable(const char *buf, int size) return pr_var(hdcp_enc_mode, index); if (set_pr_var(tmpbuf, hbr_force_8ch, value, &index, ret)) return pr_var(hbr_force_8ch, index); + if (set_pr_var(tmpbuf, cdr_lock_level, value, &index, ret)) + return pr_var(cdr_lock_level, index); return 0; } @@ -1823,6 +1825,7 @@ void rx_get_global_variable(const char *buf) pr_var(pll_rst_max, i++); pr_var(hdcp_enc_mode, i++); pr_var(hbr_force_8ch, i++); + pr_var(cdr_lock_level, i++); } void skip_frame(unsigned int cnt) @@ -2250,6 +2253,7 @@ void rx_main_state_machine(void) dvi_check_en = false; break; } + sig_stable_cnt = 0; rx.skip = 0; rx.state = FSM_SIG_READY; rx.aud_sr_stable_cnt = 0; @@ -2521,7 +2525,7 @@ unsigned int hdmirx_show_info(unsigned char *buf, int size) static void dump_phy_status(void) { - uint32_t val0, val1, val2; + uint32_t val0, val1, val2, data32; rx_pr("[PHY info]\n"); if (rx.chip_id >= CHIP_ID_TL1) { @@ -2538,6 +2542,54 @@ static void dump_phy_status(void) rx_pr("TMDS_ALIGN_STAT = 0x%x\n", hdmirx_rd_top(TOP_TMDS_ALIGN_STAT)); rx_pr("all valid = 0x%x\n", aml_phy_tmds_valid()); + + data32 = rd_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1); + data32 = data32 & 0xf0ffffff; + wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, data32); + rx_pr("0x3bc-0=%x\n", rd_reg_hhi(HHI_HDMIRX_PHY_DCHD_STAT)); + udelay(10); + data32 = ((data32 & 0xf0ffffff) | (0x2 << 24)); + wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, data32); + rx_pr("0x3bc-2=%x\n", rd_reg_hhi(HHI_HDMIRX_PHY_DCHD_STAT)); + udelay(10); + data32 = ((data32 & 0xf0ffffff) | (0x4 << 24)); + wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, data32); + rx_pr("0x3bc-4=%x\n", rd_reg_hhi(HHI_HDMIRX_PHY_DCHD_STAT)); + udelay(10); + data32 = ((data32 & 0xf0ffffff) | (0x6 << 24)); + wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, data32); + rx_pr("0x3bc-6=%x\n", rd_reg_hhi(HHI_HDMIRX_PHY_DCHD_STAT)); + udelay(10); + data32 = ((data32 & 0xf0ffffff) | (0xe << 24)); + wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, data32); + if (log_level & VIDEO_LOG) { + rx_pr("0x3bc-e=%x\n", + rd_reg_hhi(HHI_HDMIRX_PHY_DCHD_STAT)); + rx_pr("0x3bc-e=%x\n", + rd_reg_hhi(HHI_HDMIRX_PHY_DCHD_STAT)); + rx_pr("0x3bc-e=%x\n", + rd_reg_hhi(HHI_HDMIRX_PHY_DCHD_STAT)); + rx_pr("0x3bc-e=%x\n", + rd_reg_hhi(HHI_HDMIRX_PHY_DCHD_STAT)); + rx_pr("0x3bc-e=%x\n", + rd_reg_hhi(HHI_HDMIRX_PHY_DCHD_STAT)); + rx_pr("0x3bc-e=%x\n", + rd_reg_hhi(HHI_HDMIRX_PHY_DCHD_STAT)); + rx_pr("0x3bc-e=%x\n", + rd_reg_hhi(HHI_HDMIRX_PHY_DCHD_STAT)); + rx_pr("0x3bc-e=%x\n", + rd_reg_hhi(HHI_HDMIRX_PHY_DCHD_STAT)); + rx_pr("0x3bc-e=%x\n", + rd_reg_hhi(HHI_HDMIRX_PHY_DCHD_STAT)); + rx_pr("0x3bc-e=%x\n", + rd_reg_hhi(HHI_HDMIRX_PHY_DCHD_STAT)); + rx_pr("0x3bc-e=%x\n", + rd_reg_hhi(HHI_HDMIRX_PHY_DCHD_STAT)); + rx_pr("0x3bc-e=%x\n", + rd_reg_hhi(HHI_HDMIRX_PHY_DCHD_STAT)); + rx_pr("0x3bc-e=%x\n", + rd_reg_hhi(HHI_HDMIRX_PHY_DCHD_STAT)); + } } } -- 2.7.4