From b4992dbb21ff9159285ae0aec73f3d760344b0e5 Mon Sep 17 00:00:00 2001 From: Florian Hahn Date: Thu, 4 Nov 2021 13:11:17 +0100 Subject: [PATCH] [LV] Clarify uniform worklist contains instrs demanding lane 0. --- llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp index 1c6f252..b1c98ae 100644 --- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp +++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp @@ -5379,12 +5379,14 @@ void LoopVectorizationCostModel::collectLoopUniforms(ElementCount VF) { return (!I || !TheLoop->contains(I)); }; + // Worklist containing uniform instructions demanding lane 0. SetVector Worklist; BasicBlock *Latch = TheLoop->getLoopLatch(); - // Instructions that are scalar with predication must not be considered - // uniform after vectorization, because that would create an erroneous - // replicating region where only a single instance out of VF should be formed. + // Add uniform instructions demanding lane 0 to the worklist. Instructions + // that are scalar with predication must not be considered uniform after + // vectorization, because that would create an erroneous replicating region + // where only a single instance out of VF should be formed. // TODO: optimize such seldom cases if found important, see PR40816. auto addToWorklistIfAllowed = [&](Instruction *I) -> void { if (isOutOfScope(I)) { -- 2.7.4