From b4484d62ade413d59024b7b8d192d4b68b55ca03 Mon Sep 17 00:00:00 2001 From: Daniel Sanders Date: Thu, 27 Nov 2014 17:28:10 +0000 Subject: [PATCH] [mips] Add synci instruction. Patch by Amaury Pouly Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6421 llvm-svn: 222899 --- .../Target/Mips/Disassembler/MipsDisassembler.cpp | 20 +++++++++++++++++++ llvm/lib/Target/Mips/MipsInstrFormats.td | 14 +++++++++++++ llvm/lib/Target/Mips/MipsInstrInfo.td | 23 +++++++++++++++++++++- llvm/test/MC/Disassembler/Mips/mips32r2.txt | 3 +++ llvm/test/MC/Disassembler/Mips/mips32r2_le.txt | 3 +++ llvm/test/MC/Mips/mips32r2/valid-xfail.s | 1 - llvm/test/MC/Mips/mips32r2/valid.s | 1 + llvm/test/MC/Mips/mips64r2/valid-xfail.s | 1 - 8 files changed, 63 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp index a4fc32e..58a857b 100644 --- a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -252,6 +252,11 @@ static DecodeStatus DecodeCacheOp(MCInst &Inst, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeSyncI(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); + static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); @@ -1065,6 +1070,21 @@ static DecodeStatus DecodeCacheOp(MCInst &Inst, return MCDisassembler::Success; } +static DecodeStatus DecodeSyncI(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder) { + int Offset = SignExtend32<16>(Insn & 0xffff); + unsigned Base = fieldFromInstruction(Insn, 21, 5); + + Base = getReg(Decoder, Mips::GPR32RegClassID, Base); + + Inst.addOperand(MCOperand::CreateReg(Base)); + Inst.addOperand(MCOperand::CreateImm(Offset)); + + return MCDisassembler::Success; +} + static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10)); diff --git a/llvm/lib/Target/Mips/MipsInstrFormats.td b/llvm/lib/Target/Mips/MipsInstrFormats.td index 5c91fbc..d8dae25 100644 --- a/llvm/lib/Target/Mips/MipsInstrFormats.td +++ b/llvm/lib/Target/Mips/MipsInstrFormats.td @@ -411,6 +411,20 @@ class SYNC_FM : StdArch { let Inst{5-0} = 0xf; } +class SYNCI_FM : StdArch { + // Produced by the mem_simm16 address as reg << 16 | imm (see getMemEncoding). + bits<21> addr; + bits<5> rs = addr{20-16}; + bits<16> offset = addr{15-0}; + + bits<32> Inst; + + let Inst{31-26} = 0b000001; + let Inst{25-21} = rs; + let Inst{20-16} = 0b11111; + let Inst{15-0} = offset; +} + class MULT_FM op, bits<6> funct> : StdArch { bits<5> rs; bits<5> rt; diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td index 73ebeff5..ae3aab0 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsInstrInfo.td @@ -425,7 +425,14 @@ def MipsMemSimm11AsmOperand : AsmOperandClass { let RenderMethod = "addMemOperands"; let ParserMethod = "parseMemOperand"; let PredicateMethod = "isMemWithSimmOffset<11>"; - //let DiagnosticType = "Simm11"; +} + +def MipsMemSimm16AsmOperand : AsmOperandClass { + let Name = "MemOffsetSimm16"; + let SuperClasses = [MipsMemAsmOperand]; + let RenderMethod = "addMemOperands"; + let ParserMethod = "parseMemOperand"; + let PredicateMethod = "isMemWithSimmOffset<16>"; } def MipsInvertedImmoperand : AsmOperandClass { @@ -470,6 +477,12 @@ def mem_simm11 : mem_generic { let ParserMatchClass = MipsMemSimm11AsmOperand; } +def mem_simm16 : mem_generic { + let MIOperandInfo = (ops ptr_rc, simm16); + let EncoderMethod = "getMemEncoding"; + let ParserMatchClass = MipsMemSimm16AsmOperand; +} + def mem_ea : Operand { let PrintMethod = "printMemOperandEA"; let MIOperandInfo = (ops ptr_rc, simm16); @@ -860,6 +873,13 @@ class SYNC_FT : InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)], NoItinerary, FrmOther, opstr>; +class SYNCI_FT : + InstSE<(outs), (ins mem_simm16:$addr), !strconcat(opstr, "\t$addr"), [], + NoItinerary, FrmOther, opstr> { + let hasSideEffects = 1; + let DecoderMethod = "DecodeSyncI"; +} + let hasSideEffects = 1 in class TEQ_FT : InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_), @@ -1209,6 +1229,7 @@ let DecoderNamespace = "COP3_" in { } def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM, ISA_MIPS32; +def SYNCI : MMRel, SYNCI_FT<"synci">, SYNCI_FM, ISA_MIPS32R2; def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>, ISA_MIPS2; def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>, ISA_MIPS2; diff --git a/llvm/test/MC/Disassembler/Mips/mips32r2.txt b/llvm/test/MC/Disassembler/Mips/mips32r2.txt index 299f6f0..354ef74 100644 --- a/llvm/test/MC/Disassembler/Mips/mips32r2.txt +++ b/llvm/test/MC/Disassembler/Mips/mips32r2.txt @@ -448,3 +448,6 @@ # CHECK: xori $9, $6, 17767 0x38 0xc9 0x45 0x67 + +# CHECK: synci -6137($fp) +0x07 0xdf 0xe8 0x07 diff --git a/llvm/test/MC/Disassembler/Mips/mips32r2_le.txt b/llvm/test/MC/Disassembler/Mips/mips32r2_le.txt index 0362ca6..81a05b3 100644 --- a/llvm/test/MC/Disassembler/Mips/mips32r2_le.txt +++ b/llvm/test/MC/Disassembler/Mips/mips32r2_le.txt @@ -448,3 +448,6 @@ # CHECK: xori $9, $6, 17767 0x67 0x45 0xc9 0x38 + +# CHECK: synci 7500($19) +0x4c 0x1d 0x7f 0x06 diff --git a/llvm/test/MC/Mips/mips32r2/valid-xfail.s b/llvm/test/MC/Mips/mips32r2/valid-xfail.s index ef02d51..13385d0 100644 --- a/llvm/test/MC/Mips/mips32r2/valid-xfail.s +++ b/llvm/test/MC/Mips/mips32r2/valid-xfail.s @@ -293,7 +293,6 @@ swe $24,94($k0) swle $v1,-209($gp) swre $k0,-202($s2) - synci 20023($s0) tlbginv tlbginvf tlbgp diff --git a/llvm/test/MC/Mips/mips32r2/valid.s b/llvm/test/MC/Mips/mips32r2/valid.s index 4ef5aab..97cfa36 100644 --- a/llvm/test/MC/Mips/mips32r2/valid.s +++ b/llvm/test/MC/Mips/mips32r2/valid.s @@ -233,3 +233,4 @@ trunc.w.s $f28,$f30 wsbh $k1,$9 xor $s2,$a0,$s8 + synci -15842($a2) # CHECK: synci -15842($6) # encoding: [0x04,0xdf,0xc2,0x1e] diff --git a/llvm/test/MC/Mips/mips64r2/valid-xfail.s b/llvm/test/MC/Mips/mips64r2/valid-xfail.s index 9ac47f6..3e28baa 100644 --- a/llvm/test/MC/Mips/mips64r2/valid-xfail.s +++ b/llvm/test/MC/Mips/mips64r2/valid-xfail.s @@ -297,7 +297,6 @@ swe $24,94($k0) swle $v1,-209($gp) swre $k0,-202($s2) - synci 20023($s0) tlbginv tlbginvf tlbgp -- 2.7.4