From b3e3477649eb1f4377525d5fbbd6891ee776cacc Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper@intel.com>
Date: Sat, 11 Aug 2018 06:42:51 +0000
Subject: [PATCH] [X86] Remove the AL/AX/EAX/RAX short immediate forms from the
 macro fusion shouldScheduleAdjacent. NFC

These instructions are only created by the backend during MCInst lowering.

llvm-svn: 339499
---
 llvm/lib/Target/X86/X86MacroFusion.cpp | 18 ------------------
 1 file changed, 18 deletions(-)

diff --git a/llvm/lib/Target/X86/X86MacroFusion.cpp b/llvm/lib/Target/X86/X86MacroFusion.cpp
index 29db1c6..5c09597 100644
--- a/llvm/lib/Target/X86/X86MacroFusion.cpp
+++ b/llvm/lib/Target/X86/X86MacroFusion.cpp
@@ -79,57 +79,46 @@ static bool shouldScheduleAdjacent(const TargetInstrInfo &TII,
   case X86::TEST8ri:
   case X86::TEST16ri:
   case X86::TEST32ri:
-  case X86::TEST32i32:
-  case X86::TEST64i32:
   case X86::TEST64ri32:
   case X86::TEST8mr:
   case X86::TEST16mr:
   case X86::TEST32mr:
   case X86::TEST64mr:
-  case X86::AND16i16:
   case X86::AND16ri:
   case X86::AND16ri8:
   case X86::AND16rm:
   case X86::AND16rr:
-  case X86::AND32i32:
   case X86::AND32ri:
   case X86::AND32ri8:
   case X86::AND32rm:
   case X86::AND32rr:
-  case X86::AND64i32:
   case X86::AND64ri32:
   case X86::AND64ri8:
   case X86::AND64rm:
   case X86::AND64rr:
-  case X86::AND8i8:
   case X86::AND8ri:
   case X86::AND8rm:
   case X86::AND8rr:
     return true;
-  case X86::CMP16i16:
   case X86::CMP16ri:
   case X86::CMP16ri8:
   case X86::CMP16rm:
   case X86::CMP16rr:
   case X86::CMP16mr:
-  case X86::CMP32i32:
   case X86::CMP32ri:
   case X86::CMP32ri8:
   case X86::CMP32rm:
   case X86::CMP32rr:
   case X86::CMP32mr:
-  case X86::CMP64i32:
   case X86::CMP64ri32:
   case X86::CMP64ri8:
   case X86::CMP64rm:
   case X86::CMP64rr:
   case X86::CMP64mr:
-  case X86::CMP8i8:
   case X86::CMP8ri:
   case X86::CMP8rm:
   case X86::CMP8rr:
   case X86::CMP8mr:
-  case X86::ADD16i16:
   case X86::ADD16ri:
   case X86::ADD16ri8:
   case X86::ADD16ri8_DB:
@@ -137,7 +126,6 @@ static bool shouldScheduleAdjacent(const TargetInstrInfo &TII,
   case X86::ADD16rm:
   case X86::ADD16rr:
   case X86::ADD16rr_DB:
-  case X86::ADD32i32:
   case X86::ADD32ri:
   case X86::ADD32ri8:
   case X86::ADD32ri8_DB:
@@ -145,7 +133,6 @@ static bool shouldScheduleAdjacent(const TargetInstrInfo &TII,
   case X86::ADD32rm:
   case X86::ADD32rr:
   case X86::ADD32rr_DB:
-  case X86::ADD64i32:
   case X86::ADD64ri32:
   case X86::ADD64ri32_DB:
   case X86::ADD64ri8:
@@ -153,26 +140,21 @@ static bool shouldScheduleAdjacent(const TargetInstrInfo &TII,
   case X86::ADD64rm:
   case X86::ADD64rr:
   case X86::ADD64rr_DB:
-  case X86::ADD8i8:
   case X86::ADD8ri:
   case X86::ADD8rm:
   case X86::ADD8rr:
-  case X86::SUB16i16:
   case X86::SUB16ri:
   case X86::SUB16ri8:
   case X86::SUB16rm:
   case X86::SUB16rr:
-  case X86::SUB32i32:
   case X86::SUB32ri:
   case X86::SUB32ri8:
   case X86::SUB32rm:
   case X86::SUB32rr:
-  case X86::SUB64i32:
   case X86::SUB64ri32:
   case X86::SUB64ri8:
   case X86::SUB64rm:
   case X86::SUB64rr:
-  case X86::SUB8i8:
   case X86::SUB8ri:
   case X86::SUB8rm:
   case X86::SUB8rr:
-- 
2.7.4