From b3ddadfa28315c6417866eac35a3aee67fc06aa3 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Fri, 4 Oct 2019 09:35:32 +0100 Subject: [PATCH] arm64: dts: renesas: r8a774b1: Add PCIe device nodes This patch adds PCIe{0,1} device nodes for R8A774B1 SoC. Signed-off-by: Fabrizio Castro Reviewed-by: Andrew Murray Link: https://lore.kernel.org/r/1570178133-21532-7-git-send-email-fabrizio.castro@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 42 +++++++++++++++++++++++++++++-- 1 file changed, 40 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index 3bd0b47..0163b28 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -1304,19 +1304,57 @@ }; pciec0: pcie@fe000000 { + compatible = "renesas,pcie-r8a774b1", + "renesas,pcie-rcar-gen3"; reg = <0 0xfe000000 0 0x80000>; #address-cells = <3>; #size-cells = <2>; bus-range = <0x00 0xff>; - /* placeholder */ + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 + 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 + 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 + 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + interrupts = , + , + ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 319>; + status = "disabled"; }; pciec1: pcie@ee800000 { + compatible = "renesas,pcie-r8a774b1", + "renesas,pcie-rcar-gen3"; reg = <0 0xee800000 0 0x80000>; #address-cells = <3>; #size-cells = <2>; bus-range = <0x00 0xff>; - /* placeholder */ + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000 + 0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000 + 0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000 + 0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + interrupts = , + , + ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 318>; + status = "disabled"; }; fdp1@fe940000 { -- 2.7.4