From b3cece13cf42bf22ded3505068de2715b6d84ea6 Mon Sep 17 00:00:00 2001 From: Bill Schmidt Date: Thu, 7 Feb 2013 20:33:57 +0000 Subject: [PATCH] Constrain PowerPC autovectorization to fix bug 15041. Certain vector operations don't vectorize well with the current PowerPC implementation. Element insert/extract performs poorly without VSX support because Altivec requires going through memory. SREM, UREM, and VSELECT all produce bad scalar code. There's a lot of work to do for the cost model before autovectorization will be tuned well, and this is not an attempt to address the larger problem. llvm-svn: 174660 --- llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp index 88b63e6..f57d764 100644 --- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp @@ -194,6 +194,25 @@ unsigned PPCTTI::getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) const { assert(Val->isVectorTy() && "This must be a vector type"); + const unsigned Awful = 1000; + + // Vector element insert/extract with Altivec is very expensive. + // Until VSX is available, avoid vectorizing loops that require + // these operations. + if (Opcode == ISD::EXTRACT_VECTOR_ELT || + Opcode == ISD::INSERT_VECTOR_ELT) + return Awful; + + // We don't vectorize SREM/UREM so well. Constrain the vectorizer + // for those as well. + if (Opcode == ISD::SREM || Opcode == ISD::UREM) + return Awful; + + // VSELECT is not yet implemented, leading to use of insert/extract + // and ISEL, hence not a good idea. + if (Opcode == ISD::VSELECT) + return Awful; + return TargetTransformInfo::getVectorInstrCost(Opcode, Val, Index); } -- 2.7.4