From b3bd7328355f2ca7403debe8ca6fdf7b84aaa413 Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Tue, 17 May 2022 12:12:46 +0200 Subject: [PATCH] [JumpThreading] Regenerate test checks (NFC) --- llvm/test/Transforms/JumpThreading/select.ll | 347 ++++++++++++++++++++------- 1 file changed, 265 insertions(+), 82 deletions(-) diff --git a/llvm/test/Transforms/JumpThreading/select.ll b/llvm/test/Transforms/JumpThreading/select.ll index 4309a1b..392cdd3 100644 --- a/llvm/test/Transforms/JumpThreading/select.ll +++ b/llvm/test/Transforms/JumpThreading/select.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt -S -jump-threading < %s | FileCheck %s declare void @foo() @@ -10,10 +11,21 @@ declare void @quux() ; Mostly theoretical since instruction combining simplifies all selects of ; booleans where at least one operand is true/false/undef. -; CHECK-LABEL: @test_br( -; CHECK-NEXT: entry: -; CHECK-NEXT: br i1 %cond, label %L1, define void @test_br(i1 %cond, i1 %value) nounwind { +; CHECK-LABEL: @test_br( +; CHECK-NEXT: entry: +; CHECK-NEXT: br i1 [[COND:%.*]], label [[L1:%.*]], label [[L0:%.*]] +; CHECK: L0: +; CHECK-NEXT: call void @baz() +; CHECK-NEXT: [[EXPR:%.*]] = select i1 [[COND]], i1 true, i1 [[VALUE:%.*]] +; CHECK-NEXT: br i1 [[EXPR]], label [[L1]], label [[L2:%.*]] +; CHECK: L1: +; CHECK-NEXT: call void @foo() +; CHECK-NEXT: ret void +; CHECK: L2: +; CHECK-NEXT: call void @bar() +; CHECK-NEXT: ret void +; entry: br i1 %cond, label %L0, label %L3 L0: @@ -34,10 +46,27 @@ L3: ; Jump threading of switch with select as condition. -; CHECK-LABEL: @test_switch( -; CHECK-NEXT: entry: -; CHECK-NEXT: br i1 %cond, label %L1, define void @test_switch(i1 %cond, i8 %value) nounwind { +; CHECK-LABEL: @test_switch( +; CHECK-NEXT: entry: +; CHECK-NEXT: br i1 [[COND:%.*]], label [[L1:%.*]], label [[L0:%.*]] +; CHECK: L0: +; CHECK-NEXT: call void @quux() +; CHECK-NEXT: [[EXPR:%.*]] = select i1 [[COND]], i8 1, i8 [[VALUE:%.*]] +; CHECK-NEXT: switch i8 [[EXPR]], label [[L3:%.*]] [ +; CHECK-NEXT: i8 1, label [[L1]] +; CHECK-NEXT: i8 2, label [[L2:%.*]] +; CHECK-NEXT: ] +; CHECK: L1: +; CHECK-NEXT: call void @foo() +; CHECK-NEXT: ret void +; CHECK: L2: +; CHECK-NEXT: call void @bar() +; CHECK-NEXT: ret void +; CHECK: L3: +; CHECK-NEXT: call void @baz() +; CHECK-NEXT: ret void +; entry: br i1 %cond, label %L0, label %L4 L0: @@ -69,10 +98,17 @@ L4: ; Jump threading of indirectbr with select as address. -; CHECK-LABEL: @test_indirectbr( -; CHECK-NEXT: entry: -; CHECK-NEXT: br i1 %cond, label %L1, label %L3 define void @test_indirectbr(i1 %cond, i8* %address) nounwind { +; CHECK-LABEL: @test_indirectbr( +; CHECK-NEXT: entry: +; CHECK-NEXT: br i1 [[COND:%.*]], label [[L1:%.*]], label [[L3:%.*]] +; CHECK: L1: +; CHECK-NEXT: call void @foo() +; CHECK-NEXT: ret void +; CHECK: L3: +; CHECK-NEXT: call void @baz() +; CHECK-NEXT: ret void +; entry: br i1 %cond, label %L0, label %L3 L0: @@ -95,11 +131,20 @@ L3: ; duplication threshold for cases where indirectbr is being threaded ; through. -; CHECK-LABEL: @test_indirectbr_thresh( -; CHECK-NEXT: entry: -; CHECK-NEXT: br i1 %cond, label %L1, label %L3 -; CHECK-NOT: indirectbr define void @test_indirectbr_thresh(i1 %cond, i8* %address) nounwind { +; CHECK-LABEL: @test_indirectbr_thresh( +; CHECK-NEXT: entry: +; CHECK-NEXT: br i1 [[COND:%.*]], label [[L1:%.*]], label [[L3:%.*]] +; CHECK: L1: +; CHECK-NEXT: call void @quux() +; CHECK-NEXT: call void @quux() +; CHECK-NEXT: call void @quux() +; CHECK-NEXT: call void @foo() +; CHECK-NEXT: ret void +; CHECK: L3: +; CHECK-NEXT: call void @baz() +; CHECK-NEXT: ret void +; entry: br i1 %cond, label %L0, label %L3 L0: @@ -123,13 +168,33 @@ L3: ; A more complicated case: the condition is a select based on a comparison. -; CHECK-LABEL: @test_switch_cmp( -; CHECK-NEXT: entry: -; CHECK-NEXT: br i1 %cond, label %L0, label %[[THREADED:[A-Za-z.0-9]+]] -; CHECK: [[THREADED]]: -; CHECK-NEXT: call void @quux -; CHECK-NEXT: br label %L1 define void @test_switch_cmp(i1 %cond, i32 %val, i8 %value) nounwind { +; CHECK-LABEL: @test_switch_cmp( +; CHECK-NEXT: entry: +; CHECK-NEXT: br i1 [[COND:%.*]], label [[L0:%.*]], label [[L0_THREAD:%.*]] +; CHECK: L0: +; CHECK-NEXT: [[VAL_PHI:%.*]] = phi i32 [ [[VAL:%.*]], [[ENTRY:%.*]] ] +; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[VAL_PHI]], 0 +; CHECK-NEXT: br i1 [[CMP]], label [[L1:%.*]], label [[TMP0:%.*]] +; CHECK: 0: +; CHECK-NEXT: [[TMP1:%.*]] = phi i8 [ [[VALUE:%.*]], [[L0]] ] +; CHECK-NEXT: switch i8 [[TMP1]], label [[L3:%.*]] [ +; CHECK-NEXT: i8 1, label [[L1]] +; CHECK-NEXT: i8 2, label [[L2:%.*]] +; CHECK-NEXT: ] +; CHECK: L1: +; CHECK-NEXT: call void @foo() +; CHECK-NEXT: ret void +; CHECK: L2: +; CHECK-NEXT: call void @bar() +; CHECK-NEXT: ret void +; CHECK: L3: +; CHECK-NEXT: call void @baz() +; CHECK-NEXT: ret void +; CHECK: L0.thread: +; CHECK-NEXT: call void @quux() +; CHECK-NEXT: br label [[L1]] +; entry: br i1 %cond, label %L0, label %L4 L0: @@ -154,22 +219,32 @@ L4: ; Make sure the edge value of %0 from entry to L2 includes 0 and L3 is ; reachable. -; CHECK: test_switch_default -; CHECK: entry: -; CHECK: load -; CHECK: switch -; CHECK: [[THREADED:[A-Za-z.0-9]+]]: -; CHECK: store -; CHECK: br -; CHECK: L2: -; CHECK-SAME: preds = %entry, %entry -; CHECK-NEXT: phi i32 define void @test_switch_default(i32* nocapture %status) nounwind { +; CHECK-LABEL: @test_switch_default( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[STATUS:%.*]], align 4 +; CHECK-NEXT: switch i32 [[TMP0]], label [[L2:%.*]] [ +; CHECK-NEXT: i32 5061, label [[L2_THREAD:%.*]] +; CHECK-NEXT: i32 0, label [[L2]] +; CHECK-NEXT: ] +; CHECK: L2.thread: +; CHECK-NEXT: store i32 10025, i32* [[STATUS]], align 4 +; CHECK-NEXT: br label [[L4:%.*]] +; CHECK: L2: +; CHECK-NEXT: [[TMP1:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[TMP0]], [[ENTRY]] ] +; CHECK-NEXT: [[CMP57_I:%.*]] = icmp eq i32 [[TMP1]], 0 +; CHECK-NEXT: br i1 [[CMP57_I]], label [[L3:%.*]], label [[L4]] +; CHECK: L3: +; CHECK-NEXT: store i32 10000, i32* [[STATUS]], align 4 +; CHECK-NEXT: br label [[L4]] +; CHECK: L4: +; CHECK-NEXT: ret void +; entry: %0 = load i32, i32* %status, align 4 switch i32 %0, label %L2 [ - i32 5061, label %L1 - i32 0, label %L2 + i32 5061, label %L1 + i32 0, label %L2 ] L1: @@ -190,6 +265,25 @@ L4: } define void @unfold1(double %x, double %y) nounwind { +; CHECK-LABEL: @unfold1( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[SUB:%.*]] = fsub double [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[CMP:%.*]] = fcmp ogt double [[SUB]], 1.000000e+01 +; CHECK-NEXT: br i1 [[CMP]], label [[COND_END4:%.*]], label [[COND_FALSE:%.*]] +; CHECK: cond.false: +; CHECK-NEXT: [[ADD:%.*]] = fadd double [[X]], [[Y]] +; CHECK-NEXT: [[CMP1:%.*]] = fcmp ogt double [[ADD]], 1.000000e+01 +; CHECK-NEXT: br i1 [[CMP1]], label [[COND_END4]], label [[IF_THEN:%.*]] +; CHECK: cond.end4: +; CHECK-NEXT: [[COND5:%.*]] = phi double [ [[SUB]], [[ENTRY:%.*]] ], [ [[ADD]], [[COND_FALSE]] ] +; CHECK-NEXT: [[CMP6:%.*]] = fcmp oeq double [[COND5]], 0.000000e+00 +; CHECK-NEXT: br i1 [[CMP6]], label [[IF_THEN]], label [[IF_END:%.*]] +; CHECK: if.then: +; CHECK-NEXT: call void @foo() +; CHECK-NEXT: br label [[IF_END]] +; CHECK: if.end: +; CHECK-NEXT: ret void +; entry: %sub = fsub double %x, %y %cmp = fcmp ogt double %sub, 1.000000e+01 @@ -213,15 +307,29 @@ if.then: ; preds = %cond.end4 if.end: ; preds = %if.then, %cond.end4 ret void -; CHECK-LABEL: @unfold1 -; CHECK: br i1 %cmp, label %cond.end4, label %cond.false -; CHECK: br i1 %cmp1, label %cond.end4, label %if.then -; CHECK: br i1 %cmp6, label %if.then, label %if.end -; CHECK: br label %if.end } define void @unfold2(i32 %x, i32 %y) nounwind { +; CHECK-LABEL: @unfold2( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[SUB]], 10 +; CHECK-NEXT: br i1 [[CMP]], label [[IF_END:%.*]], label [[COND_FALSE:%.*]] +; CHECK: cond.false: +; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[X]], [[Y]] +; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[ADD]], 10 +; CHECK-NEXT: br i1 [[CMP1]], label [[IF_THEN:%.*]], label [[COND_END4:%.*]] +; CHECK: cond.end4: +; CHECK-NEXT: [[COND5:%.*]] = phi i32 [ [[ADD]], [[COND_FALSE]] ] +; CHECK-NEXT: [[CMP6:%.*]] = icmp eq i32 [[COND5]], 0 +; CHECK-NEXT: br i1 [[CMP6]], label [[IF_THEN]], label [[IF_END]] +; CHECK: if.then: +; CHECK-NEXT: call void @foo() +; CHECK-NEXT: br label [[IF_END]] +; CHECK: if.end: +; CHECK-NEXT: ret void +; entry: %sub = sub nsw i32 %x, %y %cmp = icmp sgt i32 %sub, 10 @@ -245,15 +353,33 @@ if.then: ; preds = %cond.end4 if.end: ; preds = %if.then, %cond.end4 ret void -; CHECK-LABEL: @unfold2 -; CHECK: br i1 %cmp, label %if.end, label %cond.false -; CHECK: br i1 %cmp1, label %if.then, label %cond.end4 -; CHECK: br i1 %cmp6, label %if.then, label %if.end -; CHECK: br label %if.end } define i32 @unfold3(i32 %u, i32 %v, i32 %w, i32 %x, i32 %y, i32 %z, i32 %j) nounwind { +; CHECK-LABEL: @unfold3( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[ADD3:%.*]] = add nsw i32 [[J:%.*]], 2 +; CHECK-NEXT: [[CMP_I:%.*]] = icmp slt i32 [[U:%.*]], [[V:%.*]] +; CHECK-NEXT: br i1 [[CMP_I]], label [[DOTEXIT_THREAD3:%.*]], label [[COND_FALSE_I:%.*]] +; CHECK: cond.false.i: +; CHECK-NEXT: [[CMP4_I:%.*]] = icmp sgt i32 [[U]], [[V]] +; CHECK-NEXT: br i1 [[CMP4_I]], label [[DOTEXIT_THREAD:%.*]], label [[COND_FALSE_6_I:%.*]] +; CHECK: cond.false.6.i: +; CHECK-NEXT: [[CMP8_I:%.*]] = icmp slt i32 [[W:%.*]], [[X:%.*]] +; CHECK-NEXT: br i1 [[CMP8_I]], label [[DOTEXIT_THREAD3]], label [[COND_FALSE_10_I:%.*]] +; CHECK: cond.false.10.i: +; CHECK-NEXT: [[CMP13_I:%.*]] = icmp sgt i32 [[W]], [[X]] +; CHECK-NEXT: br i1 [[CMP13_I]], label [[DOTEXIT_THREAD]], label [[DOTEXIT:%.*]] +; CHECK: .exit: +; CHECK-NEXT: [[PHITMP:%.*]] = icmp sge i32 [[Y:%.*]], [[Z:%.*]] +; CHECK-NEXT: br i1 [[PHITMP]], label [[DOTEXIT_THREAD]], label [[DOTEXIT_THREAD3]] +; CHECK: .exit.thread: +; CHECK-NEXT: br label [[DOTEXIT_THREAD3]] +; CHECK: .exit.thread3: +; CHECK-NEXT: [[TMP0:%.*]] = phi i32 [ [[J]], [[DOTEXIT_THREAD]] ], [ [[ADD3]], [[DOTEXIT]] ], [ [[ADD3]], [[ENTRY:%.*]] ], [ [[ADD3]], [[COND_FALSE_6_I]] ] +; CHECK-NEXT: ret i32 [[TMP0]] +; entry: %add3 = add nsw i32 %j, 2 %cmp.i = icmp slt i32 %u, %v @@ -280,16 +406,34 @@ cond.false.15.i: ; preds = %cond.false.10.i %j.add3 = select i1 %cond23.i, i32 %j, i32 %add3 ret i32 %j.add3 -; CHECK-LABEL: @unfold3 -; CHECK: br i1 %cmp.i, label %.exit.thread3, label %cond.false.i -; CHECK: br i1 %cmp4.i, label %.exit.thread, label %cond.false.6.i -; CHECK: br i1 %cmp8.i, label %.exit.thread3, label %cond.false.10.i -; CHECK: br i1 %cmp13.i, label %.exit.thread, label %.exit -; CHECK: br i1 %phitmp, label %.exit.thread, label %.exit.thread3 -; CHECK: br label %.exit.thread3 } define i32 @unfold4(i32 %u, i32 %v, i32 %w, i32 %x, i32 %y, i32 %z, i32 %j) nounwind { +; CHECK-LABEL: @unfold4( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[ADD3:%.*]] = add nsw i32 [[J:%.*]], 2 +; CHECK-NEXT: [[CMP_I:%.*]] = icmp slt i32 [[U:%.*]], [[V:%.*]] +; CHECK-NEXT: br i1 [[CMP_I]], label [[DOTEXIT_THREAD:%.*]], label [[COND_FALSE_I:%.*]] +; CHECK: cond.false.i: +; CHECK-NEXT: [[CMP4_I:%.*]] = icmp sgt i32 [[U]], [[V]] +; CHECK-NEXT: br i1 [[CMP4_I]], label [[DOTEXIT_THREAD4:%.*]], label [[COND_FALSE_6_I:%.*]] +; CHECK: cond.false.6.i: +; CHECK-NEXT: [[CMP8_I:%.*]] = icmp slt i32 [[W:%.*]], [[X:%.*]] +; CHECK-NEXT: br i1 [[CMP8_I]], label [[DOTEXIT_THREAD]], label [[COND_FALSE_10_I:%.*]] +; CHECK: cond.false.10.i: +; CHECK-NEXT: [[CMP13_I:%.*]] = icmp sgt i32 [[W]], [[X]] +; CHECK-NEXT: br i1 [[CMP13_I]], label [[DOTEXIT_THREAD4]], label [[DOTEXIT:%.*]] +; CHECK: .exit: +; CHECK-NEXT: [[CMP19_I:%.*]] = icmp sge i32 [[Y:%.*]], [[Z:%.*]] +; CHECK-NEXT: [[CONV:%.*]] = zext i1 [[CMP19_I]] to i32 +; CHECK-NEXT: [[LNOT_I18:%.*]] = icmp eq i32 [[CONV]], 1 +; CHECK-NEXT: br i1 [[LNOT_I18]], label [[DOTEXIT_THREAD]], label [[DOTEXIT_THREAD4]] +; CHECK: .exit.thread: +; CHECK-NEXT: br label [[DOTEXIT_THREAD4]] +; CHECK: .exit.thread4: +; CHECK-NEXT: [[TMP0:%.*]] = phi i32 [ [[J]], [[DOTEXIT_THREAD]] ], [ [[ADD3]], [[DOTEXIT]] ], [ [[ADD3]], [[COND_FALSE_I]] ], [ [[ADD3]], [[COND_FALSE_10_I]] ] +; CHECK-NEXT: ret i32 [[TMP0]] +; entry: %add3 = add nsw i32 %j, 2 %cmp.i = icmp slt i32 %u, %v @@ -318,16 +462,31 @@ cond.false.15.i: ; preds = %cond.false.10.i %j.add3 = select i1 %lnot.i18, i32 %j, i32 %add3 ret i32 %j.add3 -; CHECK-LABEL: @unfold4 -; CHECK: br i1 %cmp.i, label %.exit.thread, label %cond.false.i -; CHECK: br i1 %cmp4.i, label %.exit.thread4, label %cond.false.6.i -; CHECK: br i1 %cmp8.i, label %.exit.thread, label %cond.false.10.i -; CHECK: br i1 %cmp13.i, label %.exit.thread4, label %.exit -; CHECK: br i1 %lnot.i18, label %.exit.thread, label %.exit.thread4 -; CHECK: br label %.exit.thread4 } define i32 @unfold5(i32 %u, i32 %v, i32 %w, i32 %x, i32 %y, i32 %z, i32 %j) nounwind { +; CHECK-LABEL: @unfold5( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[ADD3:%.*]] = add nsw i32 [[J:%.*]], 2 +; CHECK-NEXT: [[CMP_I:%.*]] = icmp slt i32 [[U:%.*]], [[V:%.*]] +; CHECK-NEXT: br i1 [[CMP_I]], label [[DOTEXIT:%.*]], label [[COND_FALSE_I:%.*]] +; CHECK: cond.false.i: +; CHECK-NEXT: [[CMP4_I:%.*]] = icmp sgt i32 [[U]], [[V]] +; CHECK-NEXT: br i1 [[CMP4_I]], label [[DOTEXIT]], label [[COND_FALSE_6_I:%.*]] +; CHECK: cond.false.6.i: +; CHECK-NEXT: [[CMP8_I:%.*]] = icmp slt i32 [[W:%.*]], [[X:%.*]] +; CHECK-NEXT: br i1 [[CMP8_I]], label [[DOTEXIT]], label [[COND_FALSE_10_I:%.*]] +; CHECK: cond.false.10.i: +; CHECK-NEXT: [[CMP13_I:%.*]] = icmp sgt i32 [[W]], [[X]] +; CHECK-NEXT: br i1 [[CMP13_I]], label [[DOTEXIT]], label [[COND_FALSE_15_I:%.*]] +; CHECK: cond.false.15.i: +; CHECK-NEXT: [[CMP19_I:%.*]] = icmp sge i32 [[Y:%.*]], [[Z:%.*]] +; CHECK-NEXT: [[CONV:%.*]] = zext i1 [[CMP19_I]] to i32 +; CHECK-NEXT: br label [[DOTEXIT]] +; CHECK: .exit: +; CHECK-NEXT: [[TMP0:%.*]] = phi i32 [ [[J]], [[COND_FALSE_10_I]] ], [ [[CONV]], [[COND_FALSE_15_I]] ], [ 1, [[COND_FALSE_6_I]] ], [ 3, [[COND_FALSE_I]] ], [ 2, [[ENTRY:%.*]] ] +; CHECK-NEXT: ret i32 [[TMP0]] +; entry: %add3 = add nsw i32 %j, 2 %cmp.i = icmp slt i32 %u, %v @@ -356,17 +515,58 @@ cond.false.15.i: ; preds = %cond.false.10.i %j.add3 = select i1 %lnot.i18, i32 %j, i32 %cond23.i ret i32 %j.add3 -; CHECK-LABEL: @unfold5 -; CHECK: br i1 %cmp.i, label %.exit, label %cond.false.i -; CHECK: br i1 %cmp4.i, label %.exit, label %cond.false.6.i -; CHECK: br i1 %cmp8.i, label %.exit, label %cond.false.10.i -; CHECK: br i1 %cmp13.i, label %.exit, label %cond.false.15.i -; CHECK: br label %.exit } ; When a select has a constant operand in one branch, and it feeds a phi node ; and the phi node feeds a switch we unfold the select define void @test_func(i32* nocapture readonly %a, i32* nocapture readonly %b, i32* nocapture readonly %c, i32 %n) local_unnamed_addr #0 { +; CHECK-LABEL: @test_func( +; CHECK-NEXT: entry: +; CHECK-NEXT: br label [[FOR_COND:%.*]] +; CHECK: for.cond: +; CHECK-NEXT: [[I_0:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[INC:%.*]], [[SW_DEFAULT:%.*]] ] +; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[I_0]], [[N:%.*]] +; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_COND_CLEANUP:%.*]] +; CHECK: for.cond.cleanup: +; CHECK-NEXT: ret void +; CHECK: for.body: +; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[I_0]] to i64 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[A:%.*]], i64 [[TMP0]] +; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[TMP1]], 4 +; CHECK-NEXT: br i1 [[CMP1]], label [[LAND_LHS_TRUE:%.*]], label [[IF_END:%.*]] +; CHECK: land.lhs.true: +; CHECK-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds i32, i32* [[B:%.*]], i64 [[TMP0]] +; CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX3]], align 4 +; CHECK-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, i32* [[C:%.*]], i64 [[TMP0]] +; CHECK-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX5]], align 4 +; CHECK-NEXT: [[CMP6:%.*]] = icmp eq i32 [[TMP2]], [[TMP3]] +; CHECK-NEXT: br i1 [[CMP6]], label [[SW_BB:%.*]], label [[SW_BB7:%.*]] +; CHECK: if.end: +; CHECK-NEXT: [[LOCAL_VAR_0:%.*]] = phi i32 [ [[TMP1]], [[FOR_BODY]] ] +; CHECK-NEXT: switch i32 [[LOCAL_VAR_0]], label [[SW_DEFAULT]] [ +; CHECK-NEXT: i32 2, label [[SW_BB]] +; CHECK-NEXT: i32 4, label [[SW_BB7]] +; CHECK-NEXT: i32 5, label [[SW_BB8:%.*]] +; CHECK-NEXT: i32 7, label [[SW_BB9:%.*]] +; CHECK-NEXT: ] +; CHECK: sw.bb: +; CHECK-NEXT: call void @foo() +; CHECK-NEXT: br label [[SW_BB7]] +; CHECK: sw.bb7: +; CHECK-NEXT: call void @bar() +; CHECK-NEXT: br label [[SW_BB8]] +; CHECK: sw.bb8: +; CHECK-NEXT: call void @baz() +; CHECK-NEXT: br label [[SW_BB9]] +; CHECK: sw.bb9: +; CHECK-NEXT: call void @quux() +; CHECK-NEXT: br label [[SW_DEFAULT]] +; CHECK: sw.default: +; CHECK-NEXT: call void @baz() +; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[I_0]], 1 +; CHECK-NEXT: br label [[FOR_COND]] +; entry: br label %for.cond @@ -397,10 +597,10 @@ land.lhs.true: ; preds = %for.body if.end: ; preds = %land.lhs.true, %for.body %local_var.0 = phi i32 [ %1, %for.body ], [ %spec.select, %land.lhs.true ] switch i32 %local_var.0, label %sw.default [ - i32 2, label %sw.bb - i32 4, label %sw.bb7 - i32 5, label %sw.bb8 - i32 7, label %sw.bb9 + i32 2, label %sw.bb + i32 4, label %sw.bb7 + i32 5, label %sw.bb8 + i32 7, label %sw.bb9 ] sw.bb: ; preds = %if.end @@ -423,23 +623,6 @@ sw.default: ; preds = %if.end, %sw.bb9 call void @baz() %inc = add nuw nsw i32 %i.0, 1 br label %for.cond - -; CHECK-LABEL: @test_func( -; CHECK: [[REG:%[0-9]+]] = load -; CHECK-NOT: select -; CHECK: br i1 -; CHECK-NOT: select -; CHECK: br i1 {{.*}}, label [[DEST1:%.*]], label [[DEST2:%.*]] - -; The following line checks existence of a phi node, and makes sure -; it only has one incoming value. To do this, we check every '%'. Note -; that REG and REG2 each contain one '%;. There is another one in the -; beginning of the incoming block name. After that there should be no other '%'. - -; CHECK: [[REG2:%.*]] = phi i32 {{[^%]*}}[[REG]]{{[^%]*%[^%]*}} -; CHECK: switch i32 [[REG2]] -; CHECK: i32 2, label [[DEST1]] -; CHECK: i32 4, label [[DEST2]] } ; FIXME: This is an invalid transform. If %b is false and %x is poison, -- 2.7.4