From b3ab26b4aa2fe242218b1c0cfae9420f2c4021fa Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Sun, 5 Feb 2023 12:31:36 -0800 Subject: [PATCH] [RISCV] Fix bug where C_ADDI_HINT_IMM_ZERO was incorrectly disassembled as C_ADDI. And was then printed as 'mv'. --- llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | 16 ++++++++++++++++ llvm/lib/Target/RISCV/RISCVInstrInfoC.td | 3 ++- llvm/test/MC/RISCV/rvc-hints-valid.s | 3 +++ 3 files changed, 21 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index 42cdd75..014d102 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -349,6 +349,10 @@ static DecodeStatus decodeFRMArg(MCInst &Inst, uint64_t Imm, int64_t Address, return MCDisassembler::Success; } +static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst &Inst, unsigned Insn, + uint64_t Address, + const MCDisassembler *Decoder); + static DecodeStatus decodeRVCInstrSImm(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder); @@ -371,6 +375,18 @@ static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, unsigned Insn, #include "RISCVGenDisassemblerTables.inc" +static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst &Inst, unsigned Insn, + uint64_t Address, + const MCDisassembler *Decoder) { + unsigned Rd = fieldFromInstruction(Insn, 7, 5); + DecodeStatus Result = DecodeGPRNoX0RegisterClass(Inst, Rd, Address, Decoder); + (void)Result; + assert(Result == MCDisassembler::Success && "Invalid register"); + Inst.addOperand(Inst.getOperand(0)); + Inst.addOperand(MCOperand::createImm(0)); + return MCDisassembler::Success; +} + static DecodeStatus decodeRVCInstrSImm(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder) { diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td index 32e89f8..d9b8239 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td @@ -629,8 +629,9 @@ def C_ADDI_HINT_IMM_ZERO : RVInst16CI<0b000, 0b01, (outs GPRNoX0:$rd_wb), "c.addi", "$rd, $imm">, Sched<[WriteIALU, ReadIALU]> { let Constraints = "$rd = $rd_wb"; + let Inst{12} = 0; let Inst{6-2} = 0; - let isAsmParserOnly = 1; + let DecoderMethod = "decodeRVCInstrRdRs1ImmZero"; } def C_LI_HINT : RVInst16CI<0b010, 0b01, (outs GPRX0:$rd), (ins simm6:$imm), diff --git a/llvm/test/MC/RISCV/rvc-hints-valid.s b/llvm/test/MC/RISCV/rvc-hints-valid.s index d75c9d0..52d3589 100644 --- a/llvm/test/MC/RISCV/rvc-hints-valid.s +++ b/llvm/test/MC/RISCV/rvc-hints-valid.s @@ -8,6 +8,9 @@ # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+c < %s \ # RUN: | llvm-objdump -M no-aliases -d -r - \ # RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+c < %s \ +# RUN: | llvm-objdump -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s # CHECK-ASM-AND-OBJ: c.nop 8 # CHECK-ASM: encoding: [0x21,0x00] -- 2.7.4