From b2f5ab6a41e32bfd8151225b6032ca869f4e142f Mon Sep 17 00:00:00 2001 From: Ilya Leoshkevich Date: Tue, 4 Apr 2023 12:11:50 +0200 Subject: [PATCH] [SystemZ] Allow any I5 in RotateSelect* For all RotateSelect* instructions, PoP says: Bits 0-1 of the I5 field (bits 32-33 of the instruction) are ignored. LLVM, however, completely prohibits using them, e.g.: error: invalid operand for instruction asm("rxsbg %[r1],%[r2],177,43,228\n" Lift this unnecessary restriction. Reviewed By: uweigand Differential Revision: https://reviews.llvm.org/D146185 --- llvm/lib/Target/SystemZ/SystemZInstrFormats.td | 6 +++--- llvm/lib/Target/SystemZ/SystemZOperands.td | 4 ---- llvm/test/MC/SystemZ/insn-bad-z196.s | 12 ------------ llvm/test/MC/SystemZ/insn-bad-zEC12.s | 6 ------ llvm/test/MC/SystemZ/insn-bad.s | 21 --------------------- llvm/test/MC/SystemZ/insn-good-z196.s | 8 ++++++++ llvm/test/MC/SystemZ/insn-good-zEC12.s | 4 ++++ llvm/test/MC/SystemZ/insn-good.s | 16 ++++++++++++++++ 8 files changed, 31 insertions(+), 46 deletions(-) diff --git a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td index e513bef..632dcd8 100644 --- a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td +++ b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td @@ -4822,7 +4822,7 @@ class RotateSelectRIEf opcode, RegisterOperand cls1, RegisterOperand cls2> : InstRIEf { let Constraints = "$R1 = $R1src"; let DisableEncoding = "$R1src"; @@ -5107,7 +5107,7 @@ class StoreRXYPseudo : Pseudo<(outs cls1:$R1), (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4, - imm32zx6:$I5), + imm32zx8:$I5), []> { let Constraints = "$R1 = $R1src"; let DisableEncoding = "$R1src"; @@ -5252,7 +5252,7 @@ class CompareAliasRI : Alias<6, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4, - imm32zx6:$I5), []> { + imm32zx8:$I5), []> { let Constraints = "$R1 = $R1src"; } diff --git a/llvm/lib/Target/SystemZ/SystemZOperands.td b/llvm/lib/Target/SystemZ/SystemZOperands.td index a883daa..1d2a6ab 100644 --- a/llvm/lib/Target/SystemZ/SystemZOperands.td +++ b/llvm/lib/Target/SystemZ/SystemZOperands.td @@ -357,10 +357,6 @@ defm imm32zx4even : Immediate(N->getZExtValue()); }], UIMM8EVEN, "U4Imm">; -defm imm32zx6 : Immediate(N->getZExtValue()); -}], NOOP_SDNodeXForm, "U6Imm">; - defm imm32sx8 : Immediate(N->getSExtValue()); }], SIMM8, "S8Imm">; diff --git a/llvm/test/MC/SystemZ/insn-bad-z196.s b/llvm/test/MC/SystemZ/insn-bad-z196.s index 04e53c3..7ac5dd9 100644 --- a/llvm/test/MC/SystemZ/insn-bad-z196.s +++ b/llvm/test/MC/SystemZ/insn-bad-z196.s @@ -1209,10 +1209,6 @@ risbgn %r1, %r2, 0, 0, 0 #CHECK: error: invalid operand -#CHECK: risbhg %r0,%r0,0,0,-1 -#CHECK: error: invalid operand -#CHECK: risbhg %r0,%r0,0,0,64 -#CHECK: error: invalid operand #CHECK: risbhg %r0,%r0,0,-1,0 #CHECK: error: invalid operand #CHECK: risbhg %r0,%r0,0,256,0 @@ -1221,18 +1217,12 @@ #CHECK: error: invalid operand #CHECK: risbhg %r0,%r0,256,0,0 - risbhg %r0,%r0,0,0,-1 - risbhg %r0,%r0,0,0,64 risbhg %r0,%r0,0,-1,0 risbhg %r0,%r0,0,256,0 risbhg %r0,%r0,-1,0,0 risbhg %r0,%r0,256,0,0 #CHECK: error: invalid operand -#CHECK: risblg %r0,%r0,0,0,-1 -#CHECK: error: invalid operand -#CHECK: risblg %r0,%r0,0,0,64 -#CHECK: error: invalid operand #CHECK: risblg %r0,%r0,0,-1,0 #CHECK: error: invalid operand #CHECK: risblg %r0,%r0,0,256,0 @@ -1241,8 +1231,6 @@ #CHECK: error: invalid operand #CHECK: risblg %r0,%r0,256,0,0 - risblg %r0,%r0,0,0,-1 - risblg %r0,%r0,0,0,64 risblg %r0,%r0,0,-1,0 risblg %r0,%r0,0,256,0 risblg %r0,%r0,-1,0,0 diff --git a/llvm/test/MC/SystemZ/insn-bad-zEC12.s b/llvm/test/MC/SystemZ/insn-bad-zEC12.s index b5cc6eb..425abfe 100644 --- a/llvm/test/MC/SystemZ/insn-bad-zEC12.s +++ b/llvm/test/MC/SystemZ/insn-bad-zEC12.s @@ -371,10 +371,6 @@ ppno %r2, %r4 #CHECK: error: invalid operand -#CHECK: risbgn %r0,%r0,0,0,-1 -#CHECK: error: invalid operand -#CHECK: risbgn %r0,%r0,0,0,64 -#CHECK: error: invalid operand #CHECK: risbgn %r0,%r0,0,-1,0 #CHECK: error: invalid operand #CHECK: risbgn %r0,%r0,0,256,0 @@ -383,8 +379,6 @@ #CHECK: error: invalid operand #CHECK: risbgn %r0,%r0,256,0,0 - risbgn %r0,%r0,0,0,-1 - risbgn %r0,%r0,0,0,64 risbgn %r0,%r0,0,-1,0 risbgn %r0,%r0,0,256,0 risbgn %r0,%r0,-1,0,0 diff --git a/llvm/test/MC/SystemZ/insn-bad.s b/llvm/test/MC/SystemZ/insn-bad.s index e616026..b0a12ab 100644 --- a/llvm/test/MC/SystemZ/insn-bad.s +++ b/llvm/test/MC/SystemZ/insn-bad.s @@ -5635,8 +5635,6 @@ #CHECK: error: invalid operand #CHECK: risbg %r0,%r0,0,0,-1 #CHECK: error: invalid operand -#CHECK: risbg %r0,%r0,0,0,64 -#CHECK: error: invalid operand #CHECK: risbg %r0,%r0,0,-1,0 #CHECK: error: invalid operand #CHECK: risbg %r0,%r0,0,256,0 @@ -5646,7 +5644,6 @@ #CHECK: risbg %r0,%r0,256,0,0 risbg %r0,%r0,0,0,-1 - risbg %r0,%r0,0,0,64 risbg %r0,%r0,0,-1,0 risbg %r0,%r0,0,256,0 risbg %r0,%r0,-1,0,0 @@ -5685,10 +5682,6 @@ rllg %r0,%r0,0(%r1,%r2) #CHECK: error: invalid operand -#CHECK: rnsbg %r0,%r0,0,0,-1 -#CHECK: error: invalid operand -#CHECK: rnsbg %r0,%r0,0,0,64 -#CHECK: error: invalid operand #CHECK: rnsbg %r0,%r0,0,-1,0 #CHECK: error: invalid operand #CHECK: rnsbg %r0,%r0,0,256,0 @@ -5697,18 +5690,12 @@ #CHECK: error: invalid operand #CHECK: rnsbg %r0,%r0,256,0,0 - rnsbg %r0,%r0,0,0,-1 - rnsbg %r0,%r0,0,0,64 rnsbg %r0,%r0,0,-1,0 rnsbg %r0,%r0,0,256,0 rnsbg %r0,%r0,-1,0,0 rnsbg %r0,%r0,256,0,0 #CHECK: error: invalid operand -#CHECK: rosbg %r0,%r0,0,0,-1 -#CHECK: error: invalid operand -#CHECK: rosbg %r0,%r0,0,0,64 -#CHECK: error: invalid operand #CHECK: rosbg %r0,%r0,0,-1,0 #CHECK: error: invalid operand #CHECK: rosbg %r0,%r0,0,256,0 @@ -5717,8 +5704,6 @@ #CHECK: error: invalid operand #CHECK: rosbg %r0,%r0,256,0,0 - rosbg %r0,%r0,0,0,-1 - rosbg %r0,%r0,0,0,64 rosbg %r0,%r0,0,-1,0 rosbg %r0,%r0,0,256,0 rosbg %r0,%r0,-1,0,0 @@ -5766,10 +5751,6 @@ rrxtr %f2, %f0, %f0, 0 #CHECK: error: invalid operand -#CHECK: rxsbg %r0,%r0,0,0,-1 -#CHECK: error: invalid operand -#CHECK: rxsbg %r0,%r0,0,0,64 -#CHECK: error: invalid operand #CHECK: rxsbg %r0,%r0,0,-1,0 #CHECK: error: invalid operand #CHECK: rxsbg %r0,%r0,0,256,0 @@ -5778,8 +5759,6 @@ #CHECK: error: invalid operand #CHECK: rxsbg %r0,%r0,256,0,0 - rxsbg %r0,%r0,0,0,-1 - rxsbg %r0,%r0,0,0,64 rxsbg %r0,%r0,0,-1,0 rxsbg %r0,%r0,0,256,0 rxsbg %r0,%r0,-1,0,0 diff --git a/llvm/test/MC/SystemZ/insn-good-z196.s b/llvm/test/MC/SystemZ/insn-good-z196.s index a3a6628..7faa04a 100644 --- a/llvm/test/MC/SystemZ/insn-good-z196.s +++ b/llvm/test/MC/SystemZ/insn-good-z196.s @@ -1777,6 +1777,8 @@ #CHECK: risbhg %r0, %r0, 0, 0, 0 # encoding: [0xec,0x00,0x00,0x00,0x00,0x5d] #CHECK: risbhg %r0, %r0, 0, 0, 63 # encoding: [0xec,0x00,0x00,0x00,0x3f,0x5d] +#CHECK: risbhg %r0, %r0, 0, 0, 64 # encoding: [0xec,0x00,0x00,0x00,0x40,0x5d] +#CHECK: risbhg %r0, %r0, 0, 0, 255 # encoding: [0xec,0x00,0x00,0x00,0xff,0x5d] #CHECK: risbhg %r0, %r0, 0, 255, 0 # encoding: [0xec,0x00,0x00,0xff,0x00,0x5d] #CHECK: risbhg %r0, %r0, 255, 0, 0 # encoding: [0xec,0x00,0xff,0x00,0x00,0x5d] #CHECK: risbhg %r0, %r15, 0, 0, 0 # encoding: [0xec,0x0f,0x00,0x00,0x00,0x5d] @@ -1785,6 +1787,8 @@ risbhg %r0,%r0,0,0,0 risbhg %r0,%r0,0,0,63 + risbhg %r0,%r0,0,0,64 + risbhg %r0,%r0,0,0,255 risbhg %r0,%r0,0,255,0 risbhg %r0,%r0,255,0,0 risbhg %r0,%r15,0,0,0 @@ -1793,6 +1797,8 @@ #CHECK: risblg %r0, %r0, 0, 0, 0 # encoding: [0xec,0x00,0x00,0x00,0x00,0x51] #CHECK: risblg %r0, %r0, 0, 0, 63 # encoding: [0xec,0x00,0x00,0x00,0x3f,0x51] +#CHECK: risblg %r0, %r0, 0, 0, 64 # encoding: [0xec,0x00,0x00,0x00,0x40,0x51] +#CHECK: risblg %r0, %r0, 0, 0, 255 # encoding: [0xec,0x00,0x00,0x00,0xff,0x51] #CHECK: risblg %r0, %r0, 0, 255, 0 # encoding: [0xec,0x00,0x00,0xff,0x00,0x51] #CHECK: risblg %r0, %r0, 255, 0, 0 # encoding: [0xec,0x00,0xff,0x00,0x00,0x51] #CHECK: risblg %r0, %r15, 0, 0, 0 # encoding: [0xec,0x0f,0x00,0x00,0x00,0x51] @@ -1801,6 +1807,8 @@ risblg %r0,%r0,0,0,0 risblg %r0,%r0,0,0,63 + risblg %r0,%r0,0,0,64 + risblg %r0,%r0,0,0,255 risblg %r0,%r0,0,255,0 risblg %r0,%r0,255,0,0 risblg %r0,%r15,0,0,0 diff --git a/llvm/test/MC/SystemZ/insn-good-zEC12.s b/llvm/test/MC/SystemZ/insn-good-zEC12.s index 1f1bfb8..c0ff722 100644 --- a/llvm/test/MC/SystemZ/insn-good-zEC12.s +++ b/llvm/test/MC/SystemZ/insn-good-zEC12.s @@ -436,6 +436,8 @@ #CHECK: risbgn %r0, %r0, 0, 0, 0 # encoding: [0xec,0x00,0x00,0x00,0x00,0x59] #CHECK: risbgn %r0, %r0, 0, 0, 63 # encoding: [0xec,0x00,0x00,0x00,0x3f,0x59] +#CHECK: risbgn %r0, %r0, 0, 0, 64 # encoding: [0xec,0x00,0x00,0x00,0x40,0x59] +#CHECK: risbgn %r0, %r0, 0, 0, 255 # encoding: [0xec,0x00,0x00,0x00,0xff,0x59] #CHECK: risbgn %r0, %r0, 0, 255, 0 # encoding: [0xec,0x00,0x00,0xff,0x00,0x59] #CHECK: risbgn %r0, %r0, 255, 0, 0 # encoding: [0xec,0x00,0xff,0x00,0x00,0x59] #CHECK: risbgn %r0, %r15, 0, 0, 0 # encoding: [0xec,0x0f,0x00,0x00,0x00,0x59] @@ -444,6 +446,8 @@ risbgn %r0,%r0,0,0,0 risbgn %r0,%r0,0,0,63 + risbgn %r0,%r0,0,0,64 + risbgn %r0,%r0,0,0,255 risbgn %r0,%r0,0,255,0 risbgn %r0,%r0,255,0,0 risbgn %r0,%r15,0,0,0 diff --git a/llvm/test/MC/SystemZ/insn-good.s b/llvm/test/MC/SystemZ/insn-good.s index e7f73c7..d837b60 100644 --- a/llvm/test/MC/SystemZ/insn-good.s +++ b/llvm/test/MC/SystemZ/insn-good.s @@ -13467,6 +13467,8 @@ #CHECK: risbg %r0, %r0, 0, 0, 0 # encoding: [0xec,0x00,0x00,0x00,0x00,0x55] #CHECK: risbg %r0, %r0, 0, 0, 63 # encoding: [0xec,0x00,0x00,0x00,0x3f,0x55] +#CHECK: risbg %r0, %r0, 0, 0, 64 # encoding: [0xec,0x00,0x00,0x00,0x40,0x55] +#CHECK: risbg %r0, %r0, 0, 0, 255 # encoding: [0xec,0x00,0x00,0x00,0xff,0x55] #CHECK: risbg %r0, %r0, 0, 255, 0 # encoding: [0xec,0x00,0x00,0xff,0x00,0x55] #CHECK: risbg %r0, %r0, 255, 0, 0 # encoding: [0xec,0x00,0xff,0x00,0x00,0x55] #CHECK: risbg %r0, %r15, 0, 0, 0 # encoding: [0xec,0x0f,0x00,0x00,0x00,0x55] @@ -13475,6 +13477,8 @@ risbg %r0,%r0,0,0,0 risbg %r0,%r0,0,0,63 + risbg %r0,%r0,0,0,64 + risbg %r0,%r0,0,0,255 risbg %r0,%r0,0,255,0 risbg %r0,%r0,255,0,0 risbg %r0,%r15,0,0,0 @@ -13535,6 +13539,8 @@ #CHECK: rnsbg %r0, %r0, 0, 0, 0 # encoding: [0xec,0x00,0x00,0x00,0x00,0x54] #CHECK: rnsbg %r0, %r0, 0, 0, 63 # encoding: [0xec,0x00,0x00,0x00,0x3f,0x54] +#CHECK: rnsbg %r0, %r0, 0, 0, 64 # encoding: [0xec,0x00,0x00,0x00,0x40,0x54] +#CHECK: rnsbg %r0, %r0, 0, 0, 255 # encoding: [0xec,0x00,0x00,0x00,0xff,0x54] #CHECK: rnsbg %r0, %r0, 0, 255, 0 # encoding: [0xec,0x00,0x00,0xff,0x00,0x54] #CHECK: rnsbg %r0, %r0, 255, 0, 0 # encoding: [0xec,0x00,0xff,0x00,0x00,0x54] #CHECK: rnsbg %r0, %r15, 0, 0, 0 # encoding: [0xec,0x0f,0x00,0x00,0x00,0x54] @@ -13543,6 +13549,8 @@ rnsbg %r0,%r0,0,0,0 rnsbg %r0,%r0,0,0,63 + rnsbg %r0,%r0,0,0,64 + rnsbg %r0,%r0,0,0,255 rnsbg %r0,%r0,0,255,0 rnsbg %r0,%r0,255,0,0 rnsbg %r0,%r15,0,0,0 @@ -13551,6 +13559,8 @@ #CHECK: rosbg %r0, %r0, 0, 0, 0 # encoding: [0xec,0x00,0x00,0x00,0x00,0x56] #CHECK: rosbg %r0, %r0, 0, 0, 63 # encoding: [0xec,0x00,0x00,0x00,0x3f,0x56] +#CHECK: rosbg %r0, %r0, 0, 0, 64 # encoding: [0xec,0x00,0x00,0x00,0x40,0x56] +#CHECK: rosbg %r0, %r0, 0, 0, 255 # encoding: [0xec,0x00,0x00,0x00,0xff,0x56] #CHECK: rosbg %r0, %r0, 0, 255, 0 # encoding: [0xec,0x00,0x00,0xff,0x00,0x56] #CHECK: rosbg %r0, %r0, 255, 0, 0 # encoding: [0xec,0x00,0xff,0x00,0x00,0x56] #CHECK: rosbg %r0, %r15, 0, 0, 0 # encoding: [0xec,0x0f,0x00,0x00,0x00,0x56] @@ -13559,6 +13569,8 @@ rosbg %r0,%r0,0,0,0 rosbg %r0,%r0,0,0,63 + rosbg %r0,%r0,0,0,64 + rosbg %r0,%r0,0,0,255 rosbg %r0,%r0,0,255,0 rosbg %r0,%r0,255,0,0 rosbg %r0,%r15,0,0,0 @@ -13625,6 +13637,8 @@ #CHECK: rxsbg %r0, %r0, 0, 0, 0 # encoding: [0xec,0x00,0x00,0x00,0x00,0x57] #CHECK: rxsbg %r0, %r0, 0, 0, 63 # encoding: [0xec,0x00,0x00,0x00,0x3f,0x57] +#CHECK: rxsbg %r0, %r0, 0, 0, 64 # encoding: [0xec,0x00,0x00,0x00,0x40,0x57] +#CHECK: rxsbg %r0, %r0, 0, 0, 255 # encoding: [0xec,0x00,0x00,0x00,0xff,0x57] #CHECK: rxsbg %r0, %r0, 0, 255, 0 # encoding: [0xec,0x00,0x00,0xff,0x00,0x57] #CHECK: rxsbg %r0, %r0, 255, 0, 0 # encoding: [0xec,0x00,0xff,0x00,0x00,0x57] #CHECK: rxsbg %r0, %r15, 0, 0, 0 # encoding: [0xec,0x0f,0x00,0x00,0x00,0x57] @@ -13633,6 +13647,8 @@ rxsbg %r0,%r0,0,0,0 rxsbg %r0,%r0,0,0,63 + rxsbg %r0,%r0,0,0,64 + rxsbg %r0,%r0,0,0,255 rxsbg %r0,%r0,0,255,0 rxsbg %r0,%r0,255,0,0 rxsbg %r0,%r15,0,0,0 -- 2.7.4