From b2cdd776e3e5a709d5904633956d3e9eaad78020 Mon Sep 17 00:00:00 2001
From: Sanjay Patel <spatel@rotateright.com>
Date: Tue, 1 Dec 2020 07:37:06 -0500
Subject: [PATCH] [InstCombine] add tests for sign-bit-shift-of-sub; NFC

---
 llvm/test/Transforms/InstCombine/ashr-lshr.ll | 136 ++++++++++++++++++++++++++
 llvm/test/Transforms/InstCombine/lshr.ll      |   1 -
 2 files changed, 136 insertions(+), 1 deletion(-)

diff --git a/llvm/test/Transforms/InstCombine/ashr-lshr.ll b/llvm/test/Transforms/InstCombine/ashr-lshr.ll
index ee90dd5..dc1deb0 100644
--- a/llvm/test/Transforms/InstCombine/ashr-lshr.ll
+++ b/llvm/test/Transforms/InstCombine/ashr-lshr.ll
@@ -434,3 +434,139 @@ define <2 x i32> @ashr_lshr_inv_vec_wrong_pred(<2 x i32> %x, <2 x i32> %y) {
   %ret = select <2 x i1> %cmp, <2 x i32> %r, <2 x i32> %l
   ret <2 x i32> %ret
 }
+
+define i32 @lshr_sub_nsw(i32 %x, i32 %y) {
+; CHECK-LABEL: @lshr_sub_nsw(
+; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[SHR:%.*]] = lshr i32 [[SUB]], 31
+; CHECK-NEXT:    ret i32 [[SHR]]
+;
+  %sub = sub nsw i32 %x, %y
+  %shr = lshr i32 %sub, 31
+  ret i32 %shr
+}
+
+define i32 @lshr_sub_wrong_amount(i32 %x, i32 %y) {
+; CHECK-LABEL: @lshr_sub_wrong_amount(
+; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[SHR:%.*]] = lshr i32 [[SUB]], 30
+; CHECK-NEXT:    ret i32 [[SHR]]
+;
+  %sub = sub nsw i32 %x, %y
+  %shr = lshr i32 %sub, 30
+  ret i32 %shr
+}
+
+define i32 @lshr_sub(i32 %x, i32 %y) {
+; CHECK-LABEL: @lshr_sub(
+; CHECK-NEXT:    [[SUB:%.*]] = sub i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[SHR:%.*]] = lshr i32 [[SUB]], 31
+; CHECK-NEXT:    ret i32 [[SHR]]
+;
+  %sub = sub i32 %x, %y
+  %shr = lshr i32 %sub, 31
+  ret i32 %shr
+}
+
+define i32 @lshr_sub_nsw_extra_use(i32 %x, i32 %y, i32* %p) {
+; CHECK-LABEL: @lshr_sub_nsw_extra_use(
+; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    store i32 [[SUB]], i32* [[P:%.*]], align 4
+; CHECK-NEXT:    [[SHR:%.*]] = lshr i32 [[SUB]], 31
+; CHECK-NEXT:    ret i32 [[SHR]]
+;
+  %sub = sub nsw i32 %x, %y
+  store i32 %sub, i32* %p
+  %shr = lshr i32 %sub, 31
+  ret i32 %shr
+}
+
+define <3 x i42> @lshr_sub_nsw_splat(<3 x i42> %x, <3 x i42> %y) {
+; CHECK-LABEL: @lshr_sub_nsw_splat(
+; CHECK-NEXT:    [[SUB:%.*]] = sub nsw <3 x i42> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[SHR:%.*]] = lshr <3 x i42> [[SUB]], <i42 41, i42 41, i42 41>
+; CHECK-NEXT:    ret <3 x i42> [[SHR]]
+;
+  %sub = sub nsw <3 x i42> %x, %y
+  %shr = lshr <3 x i42> %sub, <i42 41, i42 41, i42 41>
+  ret <3 x i42> %shr
+}
+
+define <3 x i42> @lshr_sub_nsw_splat_undef(<3 x i42> %x, <3 x i42> %y) {
+; CHECK-LABEL: @lshr_sub_nsw_splat_undef(
+; CHECK-NEXT:    [[SUB:%.*]] = sub nsw <3 x i42> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[SHR:%.*]] = lshr <3 x i42> [[SUB]], <i42 41, i42 undef, i42 41>
+; CHECK-NEXT:    ret <3 x i42> [[SHR]]
+;
+  %sub = sub nsw <3 x i42> %x, %y
+  %shr = lshr <3 x i42> %sub, <i42 41, i42 undef, i42 41>
+  ret <3 x i42> %shr
+}
+
+define i17 @ashr_sub_nsw(i17 %x, i17 %y) {
+; CHECK-LABEL: @ashr_sub_nsw(
+; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i17 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[SHR:%.*]] = ashr i17 [[SUB]], 16
+; CHECK-NEXT:    ret i17 [[SHR]]
+;
+  %sub = sub nsw i17 %x, %y
+  %shr = ashr i17 %sub, 16
+  ret i17 %shr
+}
+
+define i17 @ashr_sub_wrong_amount(i17 %x, i17 %y) {
+; CHECK-LABEL: @ashr_sub_wrong_amount(
+; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i17 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[SHR:%.*]] = ashr i17 [[SUB]], 15
+; CHECK-NEXT:    ret i17 [[SHR]]
+;
+  %sub = sub nsw i17 %x, %y
+  %shr = ashr i17 %sub, 15
+  ret i17 %shr
+}
+
+define i32 @ashr_sub(i32 %x, i32 %y) {
+; CHECK-LABEL: @ashr_sub(
+; CHECK-NEXT:    [[SUB:%.*]] = sub i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[SHR:%.*]] = ashr i32 [[SUB]], 31
+; CHECK-NEXT:    ret i32 [[SHR]]
+;
+  %sub = sub i32 %x, %y
+  %shr = ashr i32 %sub, 31
+  ret i32 %shr
+}
+
+define i32 @ashr_sub_nsw_extra_use(i32 %x, i32 %y, i32* %p) {
+; CHECK-LABEL: @ashr_sub_nsw_extra_use(
+; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    store i32 [[SUB]], i32* [[P:%.*]], align 4
+; CHECK-NEXT:    [[SHR:%.*]] = ashr i32 [[SUB]], 31
+; CHECK-NEXT:    ret i32 [[SHR]]
+;
+  %sub = sub nsw i32 %x, %y
+  store i32 %sub, i32* %p
+  %shr = ashr i32 %sub, 31
+  ret i32 %shr
+}
+
+define <3 x i43> @ashr_sub_nsw_splat(<3 x i43> %x, <3 x i43> %y) {
+; CHECK-LABEL: @ashr_sub_nsw_splat(
+; CHECK-NEXT:    [[SUB:%.*]] = sub nsw <3 x i43> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[SHR:%.*]] = ashr <3 x i43> [[SUB]], <i43 42, i43 42, i43 42>
+; CHECK-NEXT:    ret <3 x i43> [[SHR]]
+;
+  %sub = sub nsw <3 x i43> %x, %y
+  %shr = ashr <3 x i43> %sub, <i43 42, i43 42, i43 42>
+  ret <3 x i43> %shr
+}
+
+define <3 x i43> @ashr_sub_nsw_splat_undef(<3 x i43> %x, <3 x i43> %y) {
+; CHECK-LABEL: @ashr_sub_nsw_splat_undef(
+; CHECK-NEXT:    [[SUB:%.*]] = sub nsw <3 x i43> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[SHR:%.*]] = ashr <3 x i43> [[SUB]], <i43 42, i43 undef, i43 42>
+; CHECK-NEXT:    ret <3 x i43> [[SHR]]
+;
+  %sub = sub nsw <3 x i43> %x, %y
+  %shr = ashr <3 x i43> %sub, <i43 42, i43 undef, i43 42>
+  ret <3 x i43> %shr
+}
diff --git a/llvm/test/Transforms/InstCombine/lshr.ll b/llvm/test/Transforms/InstCombine/lshr.ll
index 429a826..bcc980d 100644
--- a/llvm/test/Transforms/InstCombine/lshr.ll
+++ b/llvm/test/Transforms/InstCombine/lshr.ll
@@ -259,4 +259,3 @@ define <2 x i32> @narrow_lshr_constant(<2 x i8> %x, <2 x i8> %y) {
   %sh = lshr <2 x i32> %zx, <i32 3, i32 3>
   ret <2 x i32> %sh
 }
-
-- 
2.7.4