From b297531ece896fb9ec36f001a74aef144082602b Mon Sep 17 00:00:00 2001 From: David Truby Date: Thu, 2 Sep 2021 16:59:14 +0100 Subject: [PATCH] [AArch64][sve] Prevent incorrect function call on fixed width vector The isEssentiallyExtractHighSubvector function currently calls getVectorNumElements on a type that in specific cases might be scalable. Since this function only has correct behaviour at the moment on scalable types anyway, the function can just return false when given a fixed type. Differential Revision: https://reviews.llvm.org/D109163 --- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 2 ++ .../test/CodeGen/AArch64/sve-no-typesize-warnings.ll | 20 ++++++++++++++++++++ 2 files changed, 22 insertions(+) create mode 100644 llvm/test/CodeGen/AArch64/sve-no-typesize-warnings.ll diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index ccf05dd..337c61a 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -13861,6 +13861,8 @@ static bool isEssentiallyExtractHighSubvector(SDValue N) { N = N.getOperand(0); if (N.getOpcode() != ISD::EXTRACT_SUBVECTOR) return false; + if (N.getOperand(0).getValueType().isScalableVector()) + return false; return cast(N.getOperand(1))->getAPIntValue() == N.getOperand(0).getValueType().getVectorNumElements() / 2; } diff --git a/llvm/test/CodeGen/AArch64/sve-no-typesize-warnings.ll b/llvm/test/CodeGen/AArch64/sve-no-typesize-warnings.ll new file mode 100644 index 0000000..3492d9a --- /dev/null +++ b/llvm/test/CodeGen/AArch64/sve-no-typesize-warnings.ll @@ -0,0 +1,20 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s | FileCheck %s + +target triple = "aarch64-unknown-linux-gnu" + +define <4 x i32> @sve_no_typesize_warning( %a, <4 x i16> %b) #0 { +; CHECK-LABEL: sve_no_typesize_warning: +; CHECK: // %bb.0: +; CHECK-NEXT: uaddl v0.4s, v0.4h, v1.4h +; CHECK-NEXT: ret +%a.lo = call <4 x i16> @llvm.experimental.vector.extract.v4i16.nxv8i16( %a, i64 0) +%a.lo.zext = zext <4 x i16> %a.lo to <4 x i32> +%b.zext = zext <4 x i16> %b to <4 x i32> +%add = add <4 x i32> %a.lo.zext, %b.zext +ret <4 x i32> %add +} + +declare <4 x i16> @llvm.experimental.vector.extract.v4i16.nxv8i16(, i64) + +attributes #0 = { "target-features"="+sve" } -- 2.7.4