From b26a546b2f828990c109e3fae991b5cf50c4ffdd Mon Sep 17 00:00:00 2001 From: Simon Ser Date: Fri, 9 Apr 2021 10:18:44 +0200 Subject: [PATCH] radeon/vcn: handle tiled buffers when decoding Set the swizzle mode when decoding. Add a safe-guard to make sure the provided surface isn't DCC, because we don't handle this situation. Signed-off-by: Leo Liu Signed-off-by: Simon Ser Reviewed-by: Leo Liu Part-of: --- src/gallium/drivers/radeon/radeon_vcn_dec.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c b/src/gallium/drivers/radeon/radeon_vcn_dec.c index 312934d..310eb9a 100644 --- a/src/gallium/drivers/radeon/radeon_vcn_dec.c +++ b/src/gallium/drivers/radeon/radeon_vcn_dec.c @@ -1651,8 +1651,13 @@ static struct pb_buffer *rvcn_dec_message_decode(struct radeon_decoder *dec, decode->dt_pitch = luma->surface.u.gfx9.surf_pitch * luma->surface.blk_w; decode->dt_uv_pitch = decode->dt_pitch / 2; + if (luma->surface.meta_offset) { + RVID_ERR("DCC surfaces not supported.\n"); + return NULL; + } + decode->dt_tiling_mode = 0; - decode->dt_swizzle_mode = RDECODE_SW_MODE_LINEAR; + decode->dt_swizzle_mode = luma->surface.u.gfx9.swizzle_mode; decode->dt_array_mode = RDECODE_ARRAY_MODE_LINEAR; decode->dt_field_mode = ((struct vl_video_buffer *)target)->base.interlaced; decode->dt_surf_tile_config = 0; -- 2.7.4