From b1fbfd9e4c2c4d630eb25588061b3096704fe680 Mon Sep 17 00:00:00 2001 From: Jay Foad Date: Thu, 1 Apr 2021 16:31:22 +0100 Subject: [PATCH] [AMDGPU] Small cleanup to constructRetValue and its caller. NFC. --- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 02fda2d..1d0a104 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -5835,7 +5835,7 @@ static SDValue constructRetValue(SelectionDAG &DAG, ArrayRef ResultTypes, bool IsTexFail, bool Unpacked, bool IsD16, int DMaskPop, int NumVDataDwords, - const SDLoc &DL, LLVMContext &Context) { + const SDLoc &DL) { // Determine the required return type. This is the same regardless of IsTexFail flag EVT ReqRetVT = ResultTypes[0]; int ReqRetNumElts = ReqRetVT.isVector() ? ReqRetVT.getVectorNumElements() : 1; @@ -6279,15 +6279,13 @@ SDValue SITargetLowering::lowerImage(SDValue Op, SmallVector Elt; DAG.ExtractVectorElements(SDValue(NewNode, 0), Elt, 0, 1); return DAG.getMergeValues({Elt[0], SDValue(NewNode, 1)}, DL); - } else if (!BaseOpcode->Store) { - return constructRetValue(DAG, NewNode, - OrigResultTypes, IsTexFail, - Subtarget->hasUnpackedD16VMem(), IsD16, - DMaskLanes, NumVDataDwords, DL, - *DAG.getContext()); } - - return SDValue(NewNode, 0); + if (BaseOpcode->Store) + return SDValue(NewNode, 0); + return constructRetValue(DAG, NewNode, + OrigResultTypes, IsTexFail, + Subtarget->hasUnpackedD16VMem(), IsD16, + DMaskLanes, NumVDataDwords, DL); } SDValue SITargetLowering::lowerSBuffer(EVT VT, SDLoc DL, SDValue Rsrc, -- 2.7.4