From b14ead55f44a89e41a29d26900cb655f3b2f0d80 Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Thu, 29 Jan 2015 16:55:28 +0000 Subject: [PATCH] R600/SI: Remove stray debug statements llvm-svn: 227462 --- llvm/lib/Target/R600/SIRegisterInfo.cpp | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/llvm/lib/Target/R600/SIRegisterInfo.cpp b/llvm/lib/Target/R600/SIRegisterInfo.cpp index 122e30c..0396bf3 100644 --- a/llvm/lib/Target/R600/SIRegisterInfo.cpp +++ b/llvm/lib/Target/R600/SIRegisterInfo.cpp @@ -23,7 +23,6 @@ #include "llvm/IR/Function.h" #include "llvm/IR/LLVMContext.h" -#include "llvm/Support/Debug.h" using namespace llvm; SIRegisterInfo::SIRegisterInfo(const AMDGPUSubtarget &st) @@ -140,7 +139,6 @@ void SIRegisterInfo::buildScratchLoadStore(MachineBasicBlock::iterator MI, unsigned Size = NumSubRegs * 4; if (!isUInt<12>(Offset + Size)) { - dbgs() << "Offset scavenge\n"; SOffset = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, MI, 0); if (SOffset == AMDGPU::NoRegister) { RanOutOfSGPRs = true; @@ -235,10 +233,8 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, Ctx.emitError("Ran out of VGPRs for spilling SGPR"); } - if (isM0) { - dbgs() << "Scavenge M0\n"; + if (isM0) SubReg = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, MI, 0); - } BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_READLANE_B32), SubReg) .addReg(Spill.VGPR) -- 2.7.4