From b0e50a1f5d240bc71ffc2dbdca9cc986bc370279 Mon Sep 17 00:00:00 2001 From: =?utf8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= Date: Wed, 29 Jun 2022 11:59:56 -0400 Subject: [PATCH] arm64: dts: mediatek: asurada: Add SPI NOR flash memory MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Add support for the SPI NOR flash memory present on the Asurada platform. Signed-off-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Tested-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20220629155956.1138955-20-nfraprado@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 40 ++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi index a5625b3..4b31443 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -241,6 +241,23 @@ mediatek,mic-type-2 = <2>; /* DMIC */ }; +&nor_flash { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&nor_flash_pins>; + assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6_D8>; + + flash@0 { + compatible = "winbond,w25q64jwm", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <52000000>; + spi-rx-bus-width = <2>; + spi-tx-bus-width = <2>; + }; +}; + &pcie { pinctrl-names = "default"; pinctrl-0 = <&pcie_pins>; @@ -658,6 +675,29 @@ }; }; + nor_flash_pins: nor-flash-default-pins { + pins-cs-io1 { + pinmux = , + ; + input-enable; + bias-pull-up; + drive-strength = <10>; + }; + + pins-io0 { + pinmux = ; + bias-pull-up; + drive-strength = <10>; + }; + + pins-clk { + pinmux = ; + input-enable; + bias-pull-up; + drive-strength = <10>; + }; + }; + pcie_pins: pcie-default-pins { pins-pcie-wake { pinmux = ; -- 2.7.4