From b0a473aaf84a5c0fca4a0292341de313bece37fc Mon Sep 17 00:00:00 2001 From: James Y Knight Date: Wed, 5 Oct 2016 20:54:17 +0000 Subject: [PATCH] [Sparc] Implement UMUL_LOHI and SMUL_LOHI instead of MULHS/MULHU/MUL. This is what the instruction-set actually provides, and the default expansions of the others into the lohi opcodes are good. llvm-svn: 283381 --- llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp | 13 ------------- llvm/lib/Target/Sparc/SparcISelLowering.cpp | 7 ++++--- llvm/lib/Target/Sparc/SparcInstrInfo.td | 4 ++-- llvm/test/CodeGen/SPARC/basictest.ll | 6 ++---- 4 files changed, 8 insertions(+), 22 deletions(-) diff --git a/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp index 77d44ce..a16cd32 100644 --- a/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp +++ b/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp @@ -363,19 +363,6 @@ void SparcDAGToDAGISel::Select(SDNode *N) { CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart); return; } - case ISD::MULHU: - case ISD::MULHS: { - // FIXME: Handle mul by immediate. - SDValue MulLHS = N->getOperand(0); - SDValue MulRHS = N->getOperand(1); - unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr; - SDNode *Mul = - CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::i32, MulLHS, MulRHS); - SDValue ResultHigh = SDValue(Mul, 1); - ReplaceUses(SDValue(N, 0), ResultHigh); - CurDAG->RemoveDeadNode(N); - return; - } } SelectCode(N); diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp index 5e0fe67..d6abb55 100644 --- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp +++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp @@ -1685,9 +1685,10 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM, setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); - // FIXME: Sparc provides these multiplies, but we don't have them yet. - setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); - setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); + // Expands to [SU]MUL_LOHI. + setOperationAction(ISD::MULHU, MVT::i32, Expand); + setOperationAction(ISD::MULHS, MVT::i32, Expand); + setOperationAction(ISD::MUL, MVT::i32, Expand); if (Subtarget->is64Bit()) { setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.td b/llvm/lib/Target/Sparc/SparcInstrInfo.td index 00d22cb..5a19c62 100644 --- a/llvm/lib/Target/Sparc/SparcInstrInfo.td +++ b/llvm/lib/Target/Sparc/SparcInstrInfo.td @@ -734,8 +734,8 @@ let Defs = [ICC], rd = 0 in { // Section B.18 - Multiply Instructions, p. 113 let Defs = [Y] in { - defm UMUL : F3_12np<"umul", 0b001010, IIC_iu_umul>; - defm SMUL : F3_12 <"smul", 0b001011, mul, IntRegs, i32, simm13Op, IIC_iu_smul>; + defm UMUL : F3_12<"umul", 0b001010, umullohi, IntRegs, i32, simm13Op, IIC_iu_umul>; + defm SMUL : F3_12<"smul", 0b001011, smullohi, IntRegs, i32, simm13Op, IIC_iu_smul>; } let Defs = [Y, ICC] in { diff --git a/llvm/test/CodeGen/SPARC/basictest.ll b/llvm/test/CodeGen/SPARC/basictest.ll index 889f5144..85da61a 100644 --- a/llvm/test/CodeGen/SPARC/basictest.ll +++ b/llvm/test/CodeGen/SPARC/basictest.ll @@ -71,12 +71,10 @@ define i64 @signed_multiply_32x32_64(i32 %a, i32 %b) { } ; CHECK-LABEL: unsigned_multiply_32x32_64: -;FIXME: the smul in the output is totally redundant and should not there. -; CHECK: smul %o0, %o1, %o2 -; CHECK: umul %o0, %o1, %o0 +; CHECK: umul %o0, %o1, %o1 ; CHECK: rd %y, %o0 ; CHECK: retl -; CHECK: mov %o2, %o1 +; CHECK: nop define i64 @unsigned_multiply_32x32_64(i32 %a, i32 %b) { %xa = zext i32 %a to i64 %xb = zext i32 %b to i64 -- 2.7.4