From b08e73308ec23399def414c6f6d5020496ffda9a Mon Sep 17 00:00:00 2001 From: Erik Faye-Lund Date: Thu, 4 Apr 2019 16:50:18 +0200 Subject: [PATCH] virgl: simplify virgl_texture_transfer_unmap logic There's no reason to keep an extra indentation level here, let's merge the two if-conditions. Signed-off-by: Erik Faye-Lund Reviewed-by: Gurchetan Singh --- src/gallium/drivers/virgl/virgl_texture.c | 22 +++++++++------------- 1 file changed, 9 insertions(+), 13 deletions(-) diff --git a/src/gallium/drivers/virgl/virgl_texture.c b/src/gallium/drivers/virgl/virgl_texture.c index 4d938ca..a17c094 100644 --- a/src/gallium/drivers/virgl/virgl_texture.c +++ b/src/gallium/drivers/virgl/virgl_texture.c @@ -174,19 +174,15 @@ static void virgl_texture_transfer_unmap(struct pipe_context *ctx, struct virgl_transfer *trans = virgl_transfer(transfer); struct virgl_resource *vtex = virgl_resource(transfer->resource); - if (trans->base.usage & PIPE_TRANSFER_WRITE) { - if (!(transfer->usage & PIPE_TRANSFER_FLUSH_EXPLICIT)) { - struct virgl_screen *vs = virgl_screen(ctx->screen); - - if (trans->resolve_tmp) { - vs->vws->transfer_put(vs->vws, vtex->hw_res, - &transfer->box, trans->base.stride, - trans->l_stride, trans->offset, - transfer->level); - } else { - virgl_transfer_queue_unmap(&vctx->queue, trans); - } - } + if (transfer->usage & PIPE_TRANSFER_WRITE && + (transfer->usage & PIPE_TRANSFER_FLUSH_EXPLICIT) == 0) { + if (trans->resolve_tmp) { + struct virgl_winsys *vws = virgl_screen(ctx->screen)->vws; + vws->transfer_put(vws, vtex->hw_res, &transfer->box, + trans->base.stride, trans->l_stride, + trans->offset, transfer->level); + } else + virgl_transfer_queue_unmap(&vctx->queue, trans); } if (trans->resolve_tmp) { -- 2.7.4