From b05d85350cce3f7da40cefd29305571f6230fbf7 Mon Sep 17 00:00:00 2001 From: Seungwhan Youn Date: Tue, 19 Oct 2010 18:13:11 +0900 Subject: [PATCH] ARM: S5P64X0: Set DMA clock disable as default This patch modify to DMA operation clock into disable list for default clock setting. Signed-off-by: Seungwhan Youn Acked-by: Jassi Brar Signed-off-by: Kukjin Kim --- arch/arm/mach-s5p64x0/clock-s5p6440.c | 12 ++++++------ arch/arm/mach-s5p64x0/clock-s5p6450.c | 12 ++++++------ 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c index 0d728d3..e4883dc 100644 --- a/arch/arm/mach-s5p64x0/clock-s5p6440.c +++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c @@ -153,6 +153,12 @@ static struct clk init_clocks_disable[] = { .enable = s5p64x0_hclk0_ctrl, .ctrlbit = (1 << 8), }, { + .name = "pdma", + .id = -1, + .parent = &clk_hclk_low.clk, + .enable = s5p64x0_hclk0_ctrl, + .ctrlbit = (1 << 12), + }, { .name = "hsmmc", .id = 0, .parent = &clk_hclk_low.clk, @@ -334,12 +340,6 @@ static struct clk init_clocks[] = { .enable = s5p64x0_hclk0_ctrl, .ctrlbit = (1 << 21), }, { - .name = "dma", - .id = -1, - .parent = &clk_hclk_low.clk, - .enable = s5p64x0_hclk0_ctrl, - .ctrlbit = (1 << 12), - }, { .name = "uart", .id = 0, .parent = &clk_pclk_low.clk, diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c index 1b9b0f9..7dbf3c9 100644 --- a/arch/arm/mach-s5p64x0/clock-s5p6450.c +++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c @@ -189,6 +189,12 @@ static struct clk init_clocks_disable[] = { .enable = s5p64x0_hclk0_ctrl, .ctrlbit = (1 << 3), }, { + .name = "pdma", + .id = -1, + .parent = &clk_hclk_low.clk, + .enable = s5p64x0_hclk0_ctrl, + .ctrlbit = (1 << 12), + }, { .name = "hsmmc", .id = 0, .parent = &clk_hclk_low.clk, @@ -286,12 +292,6 @@ static struct clk init_clocks[] = { .enable = s5p64x0_hclk0_ctrl, .ctrlbit = (1 << 21), }, { - .name = "dma", - .id = -1, - .parent = &clk_hclk_low.clk, - .enable = s5p64x0_hclk0_ctrl, - .ctrlbit = (1 << 12), - }, { .name = "uart", .id = 0, .parent = &clk_pclk_low.clk, -- 2.7.4