From b042edd2d3aab48fe9524381b8b445b910722d8d Mon Sep 17 00:00:00 2001 From: Egor Chesakov Date: Mon, 3 Sep 2018 20:19:50 -0700 Subject: [PATCH] Deal with cross-bitness compilation warnings Pt.2 (#19781) * Disable ASMCONSTANTS_C_ASSERT in cross-bitness scenario in src/vm/ceeload.cpp * Adjust MAXFIELDMARSHALERSIZE for cross-bitness scenario in src/vm/arm/cgencpu.h * Make ALLOC_ALIGN_CONSTANT host specific in src/inc/stdmacros.h * Make PRECODE_ALIGNMENT host specific in src/vm/arm/cgencpu.h * Disable unreachable code in src/vm/arm/stubs.cpp * Adjust CorDBIPC_BUFFER_SIZE for cross-bitness scenario in src/debug/inc/dbgipcevents.h * Disable warning C4359 in src/vm/arm/cgencpu.h * Deal with warning C4267: 'initializing': conversion from 'size_t' to 'int' in src/vm/stublink.cpp * Deal with warning C4267: 'initializing': conversion from 'size_t' to 'int' in src/vm/callingconvention.h * Disable unreachable REGDISPLAY constructor in src/inc/regdisp.h --- src/debug/inc/dbgipcevents.h | 4 ++++ src/inc/regdisp.h | 6 +++++- src/inc/stdmacros.h | 2 +- src/vm/arm/cgencpu.h | 15 ++++++++++++++- src/vm/arm/stubs.cpp | 7 ++++--- src/vm/callingconvention.h | 6 +++--- src/vm/ceeload.cpp | 2 ++ src/vm/stublink.cpp | 8 ++++---- 8 files changed, 37 insertions(+), 13 deletions(-) diff --git a/src/debug/inc/dbgipcevents.h b/src/debug/inc/dbgipcevents.h index b91bb5b..653ec0d 100644 --- a/src/debug/inc/dbgipcevents.h +++ b/src/debug/inc/dbgipcevents.h @@ -179,7 +179,11 @@ struct MSLAYOUT DebuggerIPCRuntimeOffsets // aren't any embedded buffers in the DebuggerIPCControlBlock). #if defined(DBG_TARGET_X86) || defined(DBG_TARGET_ARM) +#ifdef _WIN64 +#define CorDBIPC_BUFFER_SIZE (2096) +#else #define CorDBIPC_BUFFER_SIZE (2088) // hand tuned to ensure that ipc block in IPCHeader.h fits in 1 page. +#endif #else // !_TARGET_X86_ && !_TARGET_ARM_ // This is the size of a DebuggerIPCEvent. You will hit an assert in Cordb::Initialize() (DI\process.cpp) // if this is not defined correctly. AMD64 actually has a page size of 0x1000, not 0x2000. diff --git a/src/inc/regdisp.h b/src/inc/regdisp.h index 06ceaf2..7875edf 100644 --- a/src/inc/regdisp.h +++ b/src/inc/regdisp.h @@ -250,7 +250,7 @@ struct REGDISPLAY : public REGDISPLAY_BASE { ArmVolatileContextPointer volatileCurrContextPointers; DWORD * pPC; // processor neutral name - +#ifndef CROSSGEN_COMPILE REGDISPLAY() { // Initialize regdisplay @@ -259,6 +259,10 @@ struct REGDISPLAY : public REGDISPLAY_BASE { // Setup the pointer to ControlPC field pPC = &ControlPC; } +#else +private: + REGDISPLAY(); +#endif }; // This function tells us if the given stack pointer is in one of the frames of the functions called by the given frame diff --git a/src/inc/stdmacros.h b/src/inc/stdmacros.h index d60abf5..6a7f286 100644 --- a/src/inc/stdmacros.h +++ b/src/inc/stdmacros.h @@ -138,7 +138,7 @@ #ifndef ALLOC_ALIGN_CONSTANT -#define ALLOC_ALIGN_CONSTANT ((1< 4); } +#ifdef _MSC_VER +#pragma warning(push) +#pragma warning(disable:4359) // Prevent "warning C4359: 'UMEntryThunkCode': Alignment specifier is less than actual alignment (8), and will be ignored." in crossbitness scenario +#endif // _MSC_VER + struct DECLSPEC_ALIGN(4) UMEntryThunkCode { WORD m_code[4]; @@ -1010,6 +1019,10 @@ struct DECLSPEC_ALIGN(4) UMEntryThunkCode } }; +#ifdef _MSC_VER +#pragma warning(pop) +#endif // _MSC_VER + struct HijackArgs { union @@ -1082,7 +1095,7 @@ inline BOOL ClrFlushInstructionCache(LPCVOID pCodeAddr, size_t sizeOfCode) EXTERN_C VOID STDCALL PrecodeFixupThunk(); -#define PRECODE_ALIGNMENT CODE_SIZE_ALIGN +#define PRECODE_ALIGNMENT sizeof(void*) #define SIZEOF_PRECODE_BASE CODE_SIZE_ALIGN #define OFFSETOF_PRECODE_TYPE 0 diff --git a/src/vm/arm/stubs.cpp b/src/vm/arm/stubs.cpp index bd3ad51..d2ee3b7 100644 --- a/src/vm/arm/stubs.cpp +++ b/src/vm/arm/stubs.cpp @@ -1678,6 +1678,8 @@ VOID StubLinkerCPU::EmitShuffleThunk(ShuffleEntry *pShuffleEntryArray) ThumbEmitEpilog(); } +#ifndef CROSSGEN_COMPILE + void StubLinkerCPU::ThumbEmitCallManagedMethod(MethodDesc *pMD, bool fTailcall) { bool isRelative = MethodTable::VTableIndir2_t::isRelative @@ -1747,7 +1749,6 @@ void StubLinkerCPU::ThumbEmitCallManagedMethod(MethodDesc *pMD, bool fTailcall) } } -#ifndef CROSSGEN_COMPILE // Common code used to generate either an instantiating method stub or an unboxing stub (in the case where the // unboxing stub also needs to provide a generic instantiation parameter). The stub needs to add the // instantiation parameter provided in pHiddenArg and re-arrange the rest of the incoming arguments as a @@ -2368,7 +2369,6 @@ void TailCallFrame::InitFromContext(T_CONTEXT * pContext) } #endif // !DACCESS_COMPILE -#endif // !CROSSGEN_COMPILE void FaultingExceptionFrame::UpdateRegDisplay(const PREGDISPLAY pRD) { @@ -2527,7 +2527,8 @@ void HijackFrame::UpdateRegDisplay(const PREGDISPLAY pRD) SyncRegDisplayToCurrentContext(pRD); } -#endif +#endif // FEATURE_HIJACK +#endif // !CROSSGEN_COMPILE class UMEntryThunk * UMEntryThunk::Decode(void *pCallback) { diff --git a/src/vm/callingconvention.h b/src/vm/callingconvention.h index a653d85..c219d70 100644 --- a/src/vm/callingconvention.h +++ b/src/vm/callingconvention.h @@ -1209,7 +1209,7 @@ int ArgIteratorTemplate::GetNextOffset() // Doubles or HFAs containing doubles need the stack aligned appropriately. if (fRequiresAlign64Bit) - m_idxStack = ALIGN_UP(m_idxStack, 2); + m_idxStack = (int)ALIGN_UP(m_idxStack, 2); // Indicate the stack location of the argument to the caller. int argOfs = TransitionBlock::GetOffsetOfArgs() + m_idxStack * 4; @@ -1231,7 +1231,7 @@ int ArgIteratorTemplate::GetNextOffset() { // The argument requires 64-bit alignment. Align either the next general argument register if // we have any left. See step C.3 in the algorithm in the ABI spec. - m_idxGenReg = ALIGN_UP(m_idxGenReg, 2); + m_idxGenReg = (int)ALIGN_UP(m_idxGenReg, 2); } int argOfs = TransitionBlock::GetOffsetOfArgumentRegisters() + m_idxGenReg * 4; @@ -1262,7 +1262,7 @@ int ArgIteratorTemplate::GetNextOffset() { // The argument requires 64-bit alignment. If it is going to be passed on the stack, align // the next stack slot. See step C.6 in the algorithm in the ABI spec. - m_idxStack = ALIGN_UP(m_idxStack, 2); + m_idxStack = (int)ALIGN_UP(m_idxStack, 2); } int argOfs = TransitionBlock::GetOffsetOfArgs() + m_idxStack * 4; diff --git a/src/vm/ceeload.cpp b/src/vm/ceeload.cpp index cd9e485..b3d2d59 100644 --- a/src/vm/ceeload.cpp +++ b/src/vm/ceeload.cpp @@ -14220,8 +14220,10 @@ void Module::ExpandAll() #include "clrvarargs.h" /* for VARARG C_ASSERTs in asmconstants.h */ class CheckAsmOffsets { +#ifndef CROSSBITNESS_COMPILE #define ASMCONSTANTS_C_ASSERT(cond) static_assert(cond, #cond); #include "asmconstants.h" +#endif // CROSSBITNESS_COMPILE }; //------------------------------------------------------------------------------- diff --git a/src/vm/stublink.cpp b/src/vm/stublink.cpp index d9715b7..98e5b13 100644 --- a/src/vm/stublink.cpp +++ b/src/vm/stublink.cpp @@ -1624,7 +1624,7 @@ bool StubLinker::EmitUnwindInfo(Stub* pStub, int globalsize, LoaderHeap* pHeap) *pUnwindCodes++ = (BYTE)0xFF; // end } - int epilogUnwindCodeIndex = 0; + ptrdiff_t epilogUnwindCodeIndex = 0; //epilog differs from prolog if(m_cbStackFrame >= 4096) @@ -1659,7 +1659,7 @@ bool StubLinker::EmitUnwindInfo(Stub* pStub, int globalsize, LoaderHeap* pHeap) } // Number of 32-bit unwind codes - int codeWordsCount = (ALIGN_UP((size_t)pUnwindCodes, sizeof(void*)) - (size_t)pUnwindInfo - sizeof(DWORD))/4; + size_t codeWordsCount = (ALIGN_UP((size_t)pUnwindCodes, sizeof(void*)) - (size_t)pUnwindInfo - sizeof(DWORD))/4; _ASSERTE(epilogUnwindCodeIndex < 32); @@ -1669,8 +1669,8 @@ bool StubLinker::EmitUnwindInfo(Stub* pStub, int globalsize, LoaderHeap* pHeap) *(DWORD *)pUnwindInfo = ((functionLength) / 2) | (1 << 21) | - (epilogUnwindCodeIndex << 23)| - (codeWordsCount << 28); + ((int)epilogUnwindCodeIndex << 23)| + ((int)codeWordsCount << 28); #elif defined(_TARGET_ARM64_) if (!m_fProlog) -- 2.7.4