From b03c98d1a34ee582680a6b475d7eca52c19ccc99 Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Thu, 3 May 2018 22:38:06 +0000 Subject: [PATCH] AMDGPU: Make getSubRegFromChannel a static member of AMDGPURegisterInfo Summary: This makes is possible to have R600RegisterInfo and SIRegisterInfo not inherit from AMDGPURegisterInfo. Reviewers: arsenm, nhaehnle Reviewed By: arsenm Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D46280 llvm-svn: 331490 --- llvm/lib/Target/AMDGPU/AMDGPURegisterInfo.cpp | 2 +- llvm/lib/Target/AMDGPU/AMDGPURegisterInfo.h | 2 +- llvm/lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp | 4 ++-- llvm/lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp | 8 ++++---- llvm/lib/Target/AMDGPU/R600InstrInfo.cpp | 2 +- 5 files changed, 9 insertions(+), 9 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterInfo.cpp index df9b4c2..4200db8 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterInfo.cpp @@ -25,7 +25,7 @@ AMDGPURegisterInfo::AMDGPURegisterInfo() : AMDGPUGenRegisterInfo(0) {} // they are not supported at this time. //===----------------------------------------------------------------------===// -unsigned AMDGPURegisterInfo::getSubRegFromChannel(unsigned Channel) const { +unsigned AMDGPURegisterInfo::getSubRegFromChannel(unsigned Channel) { static const unsigned SubRegs[] = { AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, AMDGPU::sub8, AMDGPU::sub9, diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterInfo.h b/llvm/lib/Target/AMDGPU/AMDGPURegisterInfo.h index d8ef601..db2f72f 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegisterInfo.h +++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterInfo.h @@ -31,7 +31,7 @@ struct AMDGPURegisterInfo : public AMDGPUGenRegisterInfo { /// \returns the sub reg enum value for the given \p Channel /// (e.g. getSubRegFromChannel(0) -> AMDGPU::sub0) - unsigned getSubRegFromChannel(unsigned Channel) const; + static unsigned getSubRegFromChannel(unsigned Channel); void reserveRegisterTuples(BitVector &, unsigned Reg) const; }; diff --git a/llvm/lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp b/llvm/lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp index 0e788df..0fbc254 100644 --- a/llvm/lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp +++ b/llvm/lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp @@ -308,7 +308,7 @@ private: DstMI = Reg; else DstMI = TRI->getMatchingSuperReg(Reg, - TRI->getSubRegFromChannel(TRI->getHWRegChan(Reg)), + AMDGPURegisterInfo::getSubRegFromChannel(TRI->getHWRegChan(Reg)), &AMDGPU::R600_Reg128RegClass); } if (MO.isUse()) { @@ -317,7 +317,7 @@ private: SrcMI = Reg; else SrcMI = TRI->getMatchingSuperReg(Reg, - TRI->getSubRegFromChannel(TRI->getHWRegChan(Reg)), + AMDGPURegisterInfo::getSubRegFromChannel(TRI->getHWRegChan(Reg)), &AMDGPU::R600_Reg128RegClass); } } diff --git a/llvm/lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp b/llvm/lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp index ffea231..d3feafe 100644 --- a/llvm/lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp +++ b/llvm/lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp @@ -218,13 +218,13 @@ bool R600ExpandSpecialInstrsPass::runOnMachineFunction(MachineFunction &MF) { } } if (IsReduction) { - unsigned SubRegIndex = TRI.getSubRegFromChannel(Chan); + unsigned SubRegIndex = AMDGPURegisterInfo::getSubRegFromChannel(Chan); Src0 = TRI.getSubReg(Src0, SubRegIndex); Src1 = TRI.getSubReg(Src1, SubRegIndex); } else if (IsCube) { static const int CubeSrcSwz[] = {2, 2, 0, 1}; - unsigned SubRegIndex0 = TRI.getSubRegFromChannel(CubeSrcSwz[Chan]); - unsigned SubRegIndex1 = TRI.getSubRegFromChannel(CubeSrcSwz[3 - Chan]); + unsigned SubRegIndex0 = AMDGPURegisterInfo::getSubRegFromChannel(CubeSrcSwz[Chan]); + unsigned SubRegIndex1 = AMDGPURegisterInfo::getSubRegFromChannel(CubeSrcSwz[3 - Chan]); Src1 = TRI.getSubReg(Src0, SubRegIndex1); Src0 = TRI.getSubReg(Src0, SubRegIndex0); } @@ -233,7 +233,7 @@ bool R600ExpandSpecialInstrsPass::runOnMachineFunction(MachineFunction &MF) { bool Mask = false; bool NotLast = true; if (IsCube) { - unsigned SubRegIndex = TRI.getSubRegFromChannel(Chan); + unsigned SubRegIndex = AMDGPURegisterInfo::getSubRegFromChannel(Chan); DstReg = TRI.getSubReg(DstReg, SubRegIndex); } else { // Mask the write if the original instruction does not write to diff --git a/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp index 9b8cca1..02e2f40 100644 --- a/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp @@ -72,7 +72,7 @@ void R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB, if (VectorComponents > 0) { for (unsigned I = 0; I < VectorComponents; I++) { - unsigned SubRegIndex = RI.getSubRegFromChannel(I); + unsigned SubRegIndex = AMDGPURegisterInfo::getSubRegFromChannel(I); buildDefaultInstruction(MBB, MI, AMDGPU::MOV, RI.getSubReg(DestReg, SubRegIndex), RI.getSubReg(SrcReg, SubRegIndex)) -- 2.7.4