From afffb9dfb62a9eb2a6e467a3875907189e49a2d2 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Mon, 26 Sep 2011 20:42:37 -0700 Subject: [PATCH] drm/i915: All PCH refclks are 120MHz I can't find any reference clocks which run at 96MHz as seems to be indicated from the comments in this code. Signed-off-by: Keith Packard Reviewed-by: Chris Wilson --- drivers/gpu/drm/i915/intel_display.c | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 4c9684c..b072a35 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5281,16 +5281,10 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, num_connectors++; } - if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { - refclk = dev_priv->lvds_ssc_freq * 1000; - DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", - refclk / 1000); - } else { - refclk = 96000; - if (!has_edp_encoder || - intel_encoder_is_pch_edp(&has_edp_encoder->base)) - refclk = 120000; /* 120Mhz refclk */ - } + /* + * Every reference clock in a PCH system is 120MHz + */ + refclk = 120000; /* * Returns a set of divisors for the desired target clock with the given -- 2.7.4