From afa06e1828a78c127182dbddfd9ec205ef8f059e Mon Sep 17 00:00:00 2001 From: Igor Mammedov Date: Mon, 28 Dec 2015 18:02:55 +0100 Subject: [PATCH] pc: acpi: q35: move PCI0 device definition into SSDT Signed-off-by: Igor Mammedov Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/i386/acpi-build.c | 14 +++++++++----- hw/i386/q35-acpi-dsdt.dsl | 13 ------------- 2 files changed, 9 insertions(+), 18 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 29abb99..609baf4 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -1983,11 +1983,15 @@ build_ssdt(GArray *table_data, GArray *linker, build_piix4_pci0_int(ssdt); } else { sb_scope = aml_scope("_SB"); - scope = aml_scope("PCI0"); - aml_append(scope, aml_name_decl("SUPP", aml_int(0))); - aml_append(scope, aml_name_decl("CTRL", aml_int(0))); - aml_append(scope, build_q35_osc_method()); - aml_append(sb_scope, scope); + dev = aml_device("PCI0"); + aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); + aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); + aml_append(dev, aml_name_decl("_ADR", aml_int(0))); + aml_append(dev, aml_name_decl("_UID", aml_int(1))); + aml_append(dev, aml_name_decl("SUPP", aml_int(0))); + aml_append(dev, aml_name_decl("CTRL", aml_int(0))); + aml_append(dev, build_q35_osc_method()); + aml_append(sb_scope, dev); aml_append(ssdt, sb_scope); build_hpet_aml(ssdt); diff --git a/hw/i386/q35-acpi-dsdt.dsl b/hw/i386/q35-acpi-dsdt.dsl index b53663c..f234f5c 100644 --- a/hw/i386/q35-acpi-dsdt.dsl +++ b/hw/i386/q35-acpi-dsdt.dsl @@ -42,17 +42,4 @@ DefinitionBlock ( PCIB, 8, } } - - -/**************************************************************** - * PCI Bus definition - ****************************************************************/ - Scope(\_SB) { - Device(PCI0) { - Name(_HID, EisaId("PNP0A08")) - Name(_CID, EisaId("PNP0A03")) - Name(_ADR, 0x00) - Name(_UID, 1) - } - } } -- 2.7.4