From aec8da04e4d71afdd4ab3025ea34a6517435f363 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Tue, 10 Nov 2020 15:34:32 +0100 Subject: [PATCH] x86/ioapic: Correct the PCI/ISA trigger type selection PCI's default trigger type is level and ISA's is edge. The recent refactoring made it the other way round, which went unnoticed as it seems only to cause havoc on some AMD systems. Make the comment and code do the right thing again. Fixes: a27dca645d2c ("x86/io_apic: Cleanup trigger/polarity helpers") Reported-by: Tom Lendacky Reported-by: Borislav Petkov Reported-by: Qian Cai Signed-off-by: Thomas Gleixner Tested-by: Tom Lendacky Cc: David Woodhouse Link: https://lore.kernel.org/r/87d00lgu13.fsf@nanos.tec.linutronix.de --- arch/x86/kernel/apic/io_apic.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c index 0602c95..089e755 100644 --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -809,9 +809,9 @@ static bool irq_is_level(int idx) case MP_IRQTRIG_DEFAULT: /* * Conforms to spec, ie. bus-type dependent trigger - * mode. PCI defaults to egde, ISA to level. + * mode. PCI defaults to level, ISA to edge. */ - level = test_bit(bus, mp_bus_not_pci); + level = !test_bit(bus, mp_bus_not_pci); /* Take EISA into account */ return eisa_irq_is_level(idx, bus, level); case MP_IRQTRIG_EDGE: -- 2.7.4