From aec872cda0b0a6cd73a591e28d1beef6cc6f7865 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Daniel=20Sch=C3=BCrmann?= Date: Fri, 18 Sep 2020 13:48:52 +0100 Subject: [PATCH] aco: use p_split_vector for nir_op_unpack_half_* This enables the use of SDWA if possible Totals from 9933 (7.27% of 136546) affected shaders (RAVEN): VGPRs: 731764 -> 731772 (+0.00%); split: -0.00%, +0.00% CodeSize: 90944852 -> 90671472 (-0.30%); split: -0.30%, +0.00% Instrs: 17881885 -> 17867831 (-0.08%); split: -0.08%, +0.00% Cycles: 1597904072 -> 1597771260 (-0.01%); split: -0.01%, +0.00% VMEM: 1702328 -> 1697383 (-0.29%); split: +0.13%, -0.42% SMEM: 659583 -> 659049 (-0.08%); split: +0.01%, -0.09% VClause: 318024 -> 318025 (+0.00%); split: -0.00%, +0.00% SClause: 631670 -> 631707 (+0.01%); split: -0.01%, +0.01% Copies: 1504107 -> 1504626 (+0.03%); split: -0.01%, +0.04% PreVGPRs: 683153 -> 683180 (+0.00%) Reviewed-by: Rhys Perry Part-of: --- src/amd/compiler/aco_instruction_selection.cpp | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index e751107..87ff6e4 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -2629,9 +2629,12 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr) } case nir_op_unpack_half_2x16_split_x_flush_to_zero: case nir_op_unpack_half_2x16_split_x: { + Temp src = get_alu_src(ctx, instr->src[0]); + if (src.regClass() == v1) + src = bld.pseudo(aco_opcode::p_split_vector, bld.def(v2b), bld.def(v2b), src); if (dst.regClass() == v1) { assert(ctx->block->fp_mode.must_flush_denorms16_64 == (instr->op == nir_op_unpack_half_2x16_split_x_flush_to_zero)); - bld.vop1(aco_opcode::v_cvt_f32_f16, Definition(dst), get_alu_src(ctx, instr->src[0])); + bld.vop1(aco_opcode::v_cvt_f32_f16, Definition(dst), src); } else { isel_err(&instr->instr, "Unimplemented NIR instr bit size"); } @@ -2639,11 +2642,14 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr) } case nir_op_unpack_half_2x16_split_y_flush_to_zero: case nir_op_unpack_half_2x16_split_y: { + Temp src = get_alu_src(ctx, instr->src[0]); + if (src.regClass() == s1) + src = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.def(s1, scc), src, Operand(16u)); + else + src = bld.pseudo(aco_opcode::p_split_vector, bld.def(v2b), bld.def(v2b), src).def(1).getTemp(); if (dst.regClass() == v1) { assert(ctx->block->fp_mode.must_flush_denorms16_64 == (instr->op == nir_op_unpack_half_2x16_split_y_flush_to_zero)); - /* TODO: use SDWA here */ - bld.vop1(aco_opcode::v_cvt_f32_f16, Definition(dst), - bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), Operand(16u), as_vgpr(ctx, get_alu_src(ctx, instr->src[0])))); + bld.vop1(aco_opcode::v_cvt_f32_f16, Definition(dst), src); } else { isel_err(&instr->instr, "Unimplemented NIR instr bit size"); } -- 2.7.4