From ae9356e8c45ebf0192d94d7f012d529c25edd23d Mon Sep 17 00:00:00 2001
From: Krzysztof Parzyszek <kparzysz@quicinc.com>
Date: Wed, 23 Nov 2022 12:54:05 -0800
Subject: [PATCH] [Hexagon] Fix order of operands in V6_vmpyhus

The unsigned operand is second: Vdd32.w = vmpy(Vu32.h,Vv32.uh)
---
 llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp |  3 ++-
 llvm/test/CodeGen/Hexagon/autohvx/mulh.ll        | 10 +++++-----
 llvm/test/CodeGen/Hexagon/autohvx/qmul.ll        |  4 ++--
 3 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp b/llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp
index 44fb0d7..144555e 100644
--- a/llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp
@@ -1576,6 +1576,7 @@ auto HvxIdioms::createMul16(IRBuilderBase &Builder, SValue X, SValue Y) const
   if (X.Sgn == Signed) {
     V6_vmpyh = HVC.HST.getIntrinsicId(Hexagon::V6_vmpyhv);
   } else if (Y.Sgn == Signed) {
+    // In vmpyhus the second operand is unsigned
     V6_vmpyh = HVC.HST.getIntrinsicId(Hexagon::V6_vmpyhus);
   } else {
     V6_vmpyh = HVC.HST.getIntrinsicId(Hexagon::V6_vmpyuhv);
@@ -1583,7 +1584,7 @@ auto HvxIdioms::createMul16(IRBuilderBase &Builder, SValue X, SValue Y) const
 
   // i16*i16 -> i32 / interleaved
   Value *P =
-      HVC.createHvxIntrinsic(Builder, V6_vmpyh, HvxP32Ty, {X.Val, Y.Val});
+      HVC.createHvxIntrinsic(Builder, V6_vmpyh, HvxP32Ty, {Y.Val, X.Val});
   // Deinterleave
   return HVC.vdeal(Builder, HVC.sublo(Builder, P), HVC.subhi(Builder, P));
 }
diff --git a/llvm/test/CodeGen/Hexagon/autohvx/mulh.ll b/llvm/test/CodeGen/Hexagon/autohvx/mulh.ll
index 561ab4e..a4a418f 100644
--- a/llvm/test/CodeGen/Hexagon/autohvx/mulh.ll
+++ b/llvm/test/CodeGen/Hexagon/autohvx/mulh.ll
@@ -7,7 +7,7 @@ define <64 x i16> @mulhs16(<64 x i16> %a0, <64 x i16> %a1) #0 {
 ; V60-LABEL: mulhs16:
 ; V60:       // %bb.0:
 ; V60-NEXT:    {
-; V60-NEXT:     v1:0.w = vmpy(v0.h,v1.h)
+; V60-NEXT:     v1:0.w = vmpy(v1.h,v0.h)
 ; V60-NEXT:    }
 ; V60-NEXT:    {
 ; V60-NEXT:     r7 = #-4
@@ -25,7 +25,7 @@ define <64 x i16> @mulhs16(<64 x i16> %a0, <64 x i16> %a1) #0 {
 ; V65-LABEL: mulhs16:
 ; V65:       // %bb.0:
 ; V65-NEXT:    {
-; V65-NEXT:     v1:0.w = vmpy(v0.h,v1.h)
+; V65-NEXT:     v1:0.w = vmpy(v1.h,v0.h)
 ; V65-NEXT:    }
 ; V65-NEXT:    {
 ; V65-NEXT:     r7 = #-4
@@ -43,7 +43,7 @@ define <64 x i16> @mulhs16(<64 x i16> %a0, <64 x i16> %a1) #0 {
 ; V69-LABEL: mulhs16:
 ; V69:       // %bb.0:
 ; V69-NEXT:    {
-; V69-NEXT:     v1:0.w = vmpy(v0.h,v1.h)
+; V69-NEXT:     v1:0.w = vmpy(v1.h,v0.h)
 ; V69-NEXT:    }
 ; V69-NEXT:    {
 ; V69-NEXT:     r7 = #-4
@@ -69,7 +69,7 @@ define <64 x i16> @mulhu16(<64 x i16> %a0, <64 x i16> %a1) #0 {
 ; V60-LABEL: mulhu16:
 ; V60:       // %bb.0:
 ; V60-NEXT:    {
-; V60-NEXT:     v1:0.uw = vmpy(v0.uh,v1.uh)
+; V60-NEXT:     v1:0.uw = vmpy(v1.uh,v0.uh)
 ; V60-NEXT:    }
 ; V60-NEXT:    {
 ; V60-NEXT:     r7 = #-4
@@ -87,7 +87,7 @@ define <64 x i16> @mulhu16(<64 x i16> %a0, <64 x i16> %a1) #0 {
 ; V65-LABEL: mulhu16:
 ; V65:       // %bb.0:
 ; V65-NEXT:    {
-; V65-NEXT:     v1:0.uw = vmpy(v0.uh,v1.uh)
+; V65-NEXT:     v1:0.uw = vmpy(v1.uh,v0.uh)
 ; V65-NEXT:    }
 ; V65-NEXT:    {
 ; V65-NEXT:     r7 = #-4
diff --git a/llvm/test/CodeGen/Hexagon/autohvx/qmul.ll b/llvm/test/CodeGen/Hexagon/autohvx/qmul.ll
index 3ed0a70..6760875 100644
--- a/llvm/test/CodeGen/Hexagon/autohvx/qmul.ll
+++ b/llvm/test/CodeGen/Hexagon/autohvx/qmul.ll
@@ -72,7 +72,7 @@ define void @f2(ptr %a0, ptr %a1, ptr %a2) #0 {
 ; CHECK-LABEL: f2:
 ; CHECK:       // %bb.0: // %b0
 ; CHECK-NEXT:    {
-; CHECK-NEXT:     v0 = vmem(r0+#0)
+; CHECK-NEXT:     v0 = vmem(r1+#0)
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     r7 = #-4
@@ -81,7 +81,7 @@ define void @f2(ptr %a0, ptr %a1, ptr %a2) #0 {
 ; CHECK-NEXT:     r3 = #15
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    {
-; CHECK-NEXT:     v1 = vmem(r1+#0)
+; CHECK-NEXT:     v1 = vmem(r0+#0)
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     v1:0.w = vmpy(v0.h,v1.h)
-- 
2.7.4