From adf72e8549d3eb635af96a550c2dfd153212d4de Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Wed, 14 Mar 2018 21:03:09 +0000
Subject: [PATCH] [X86] Add haswell testing for PR35635 as well.

To improve complete model testing for schedulers for instructions with multiple results.

llvm-svn: 327572
---
 llvm/test/CodeGen/X86/pr35636.ll | 50 +++++++++++++++++++++++++++-------------
 1 file changed, 34 insertions(+), 16 deletions(-)

diff --git a/llvm/test/CodeGen/X86/pr35636.ll b/llvm/test/CodeGen/X86/pr35636.ll
index 70ff8d8..07fb37f 100644
--- a/llvm/test/CodeGen/X86/pr35636.ll
+++ b/llvm/test/CodeGen/X86/pr35636.ll
@@ -1,22 +1,40 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=znver1 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=haswell | FileCheck %s --check-prefix=HSW
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=znver1 | FileCheck %s --check-prefix=ZN
 
 define void @_Z15uint64_to_asciimPc(i64 %arg) {
-; CHECK-LABEL: _Z15uint64_to_asciimPc:
-; CHECK:       # %bb.0: # %bb
-; CHECK-NEXT:    movabsq $811296384146066817, %rax # imm = 0xB424DC35095CD81
-; CHECK-NEXT:    movq %rdi, %rdx
-; CHECK-NEXT:    mulxq %rax, %rax, %rcx
-; CHECK-NEXT:    shrq $42, %rcx
-; CHECK-NEXT:    imulq $281474977, %rcx, %rax # imm = 0x10C6F7A1
-; CHECK-NEXT:    shrq $20, %rax
-; CHECK-NEXT:    leal 5(%rax,%rax,4), %eax
-; CHECK-NEXT:    andl $134217727, %eax # imm = 0x7FFFFFF
-; CHECK-NEXT:    leal (%rax,%rax,4), %eax
-; CHECK-NEXT:    shrl $26, %eax
-; CHECK-NEXT:    orb $48, %al
-; CHECK-NEXT:    movb %al, (%rax)
-; CHECK-NEXT:    retq
+; HSW-LABEL: _Z15uint64_to_asciimPc:
+; HSW:       # %bb.0: # %bb
+; HSW-NEXT:    movabsq $811296384146066817, %rax # imm = 0xB424DC35095CD81
+; HSW-NEXT:    movq %rdi, %rdx
+; HSW-NEXT:    mulxq %rax, %rax, %rcx
+; HSW-NEXT:    shrq $42, %rcx
+; HSW-NEXT:    imulq $281474977, %rcx, %rax # imm = 0x10C6F7A1
+; HSW-NEXT:    shrq $20, %rax
+; HSW-NEXT:    leal (%rax,%rax,4), %eax
+; HSW-NEXT:    addl $5, %eax
+; HSW-NEXT:    andl $134217727, %eax # imm = 0x7FFFFFF
+; HSW-NEXT:    leal (%rax,%rax,4), %eax
+; HSW-NEXT:    shrl $26, %eax
+; HSW-NEXT:    orb $48, %al
+; HSW-NEXT:    movb %al, (%rax)
+; HSW-NEXT:    retq
+;
+; ZN-LABEL: _Z15uint64_to_asciimPc:
+; ZN:       # %bb.0: # %bb
+; ZN-NEXT:    movabsq $811296384146066817, %rax # imm = 0xB424DC35095CD81
+; ZN-NEXT:    movq %rdi, %rdx
+; ZN-NEXT:    mulxq %rax, %rax, %rcx
+; ZN-NEXT:    shrq $42, %rcx
+; ZN-NEXT:    imulq $281474977, %rcx, %rax # imm = 0x10C6F7A1
+; ZN-NEXT:    shrq $20, %rax
+; ZN-NEXT:    leal 5(%rax,%rax,4), %eax
+; ZN-NEXT:    andl $134217727, %eax # imm = 0x7FFFFFF
+; ZN-NEXT:    leal (%rax,%rax,4), %eax
+; ZN-NEXT:    shrl $26, %eax
+; ZN-NEXT:    orb $48, %al
+; ZN-NEXT:    movb %al, (%rax)
+; ZN-NEXT:    retq
 bb:
   %tmp = udiv i64 %arg, 100000000000000
   %tmp1 = mul nuw nsw i64 %tmp, 281474977
-- 
2.7.4