From ad21f2687dcca2199a5b2bd9b7f04486008ece16 Mon Sep 17 00:00:00 2001 From: Vedran Miletic Date: Mon, 27 Nov 2017 13:26:38 +0000 Subject: [PATCH] [AMDGPU] Add custom lowering for llvm.log{,10}.{f16,f32} intrinsics AMDGPU backend errors with "unsupported call to function" upon encountering a call to llvm.log{,10}.{f16,f32} intrinsics. This patch adds custom lowering to avoid that error on both R600 and SI. Reviewers: arsenm, jvesely Subscribers: tstellar Differential Revision: https://reviews.llvm.org/D29942 llvm-svn: 319025 --- llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 30 +++++++++ llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h | 2 + llvm/test/CodeGen/AMDGPU/llvm.log.f16.ll | 71 +++++++++++++++++++++ llvm/test/CodeGen/AMDGPU/llvm.log.ll | 89 +++++++++++++++++++++++++++ llvm/test/CodeGen/AMDGPU/llvm.log10.f16.ll | 71 +++++++++++++++++++++ llvm/test/CodeGen/AMDGPU/llvm.log10.ll | 89 +++++++++++++++++++++++++++ 6 files changed, 352 insertions(+) create mode 100644 llvm/test/CodeGen/AMDGPU/llvm.log.f16.ll create mode 100644 llvm/test/CodeGen/AMDGPU/llvm.log.ll create mode 100644 llvm/test/CodeGen/AMDGPU/llvm.log10.f16.ll create mode 100644 llvm/test/CodeGen/AMDGPU/llvm.log10.ll diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp index 0ec338e..4016686 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp @@ -13,6 +13,10 @@ // //===----------------------------------------------------------------------===// +#define AMDGPU_LOG2E_F 1.44269504088896340735992468100189214f +#define AMDGPU_LN2_F 0.693147180559945309417232121458176568f +#define AMDGPU_LN10_F 2.30258509299404568401799145468436421f + #include "AMDGPUISelLowering.h" #include "AMDGPU.h" #include "AMDGPUCallLowering.h" @@ -317,6 +321,14 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM, setOperationAction(ISD::FROUND, MVT::f32, Custom); setOperationAction(ISD::FROUND, MVT::f64, Custom); + setOperationAction(ISD::FLOG, MVT::f32, Custom); + setOperationAction(ISD::FLOG10, MVT::f32, Custom); + + if (Subtarget->has16BitInsts()) { + setOperationAction(ISD::FLOG, MVT::f16, Custom); + setOperationAction(ISD::FLOG10, MVT::f16, Custom); + } + setOperationAction(ISD::FNEARBYINT, MVT::f32, Custom); setOperationAction(ISD::FNEARBYINT, MVT::f64, Custom); @@ -487,6 +499,8 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM, setOperationAction(ISD::FEXP2, VT, Expand); setOperationAction(ISD::FLOG2, VT, Expand); setOperationAction(ISD::FREM, VT, Expand); + setOperationAction(ISD::FLOG, VT, Expand); + setOperationAction(ISD::FLOG10, VT, Expand); setOperationAction(ISD::FPOW, VT, Expand); setOperationAction(ISD::FFLOOR, VT, Expand); setOperationAction(ISD::FTRUNC, VT, Expand); @@ -1112,6 +1126,10 @@ SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, case ISD::FNEARBYINT: return LowerFNEARBYINT(Op, DAG); case ISD::FROUND: return LowerFROUND(Op, DAG); case ISD::FFLOOR: return LowerFFLOOR(Op, DAG); + case ISD::FLOG: + return LowerFLOG(Op, DAG, 1 / AMDGPU_LOG2E_F); + case ISD::FLOG10: + return LowerFLOG(Op, DAG, AMDGPU_LN2_F / AMDGPU_LN10_F); case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG); case ISD::FP_TO_FP16: return LowerFP_TO_FP16(Op, DAG); @@ -2160,6 +2178,18 @@ SDValue AMDGPUTargetLowering::LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const { return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add); } +SDValue AMDGPUTargetLowering::LowerFLOG(SDValue Op, SelectionDAG &DAG, + double Log2BaseInverted) const { + EVT VT = Op.getValueType(); + + SDLoc SL(Op); + SDValue Operand = Op.getOperand(0); + SDValue Log2Operand = DAG.getNode(ISD::FLOG2, SL, VT, Operand); + SDValue Log2BaseInvertedOperand = DAG.getConstantFP(Log2BaseInverted, SL, VT); + + return DAG.getNode(ISD::FMUL, SL, VT, Log2Operand, Log2BaseInvertedOperand); +} + static bool isCtlzOpc(unsigned Opc) { return Opc == ISD::CTLZ || Opc == ISD::CTLZ_ZERO_UNDEF; } diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h index 7e76b4a..3f8a9b1 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h @@ -57,6 +57,8 @@ protected: SDValue LowerFROUND64(SDValue Op, SelectionDAG &DAG) const; SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const; SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerFLOG(SDValue Op, SelectionDAG &Dag, + double Log2BaseInverted) const; SDValue LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) const; diff --git a/llvm/test/CodeGen/AMDGPU/llvm.log.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.log.f16.ll new file mode 100644 index 0000000..d64c0bb --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/llvm.log.f16.ll @@ -0,0 +1,71 @@ +; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=SIVI -check-prefix=FUNC %s +; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=SIVI -check-prefix=VIGFX9 -check-prefix=FUNC %s +; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 -check-prefix=VIGFX9 -check-prefix=FUNC %s + +declare half @llvm.log.f16(half %a) +declare <2 x half> @llvm.log.v2f16(<2 x half> %a) + +; FUNC-LABEL: {{^}}log_f16 +; SI: buffer_load_ushort v[[A_F16_0:[0-9]+]] +; VI: flat_load_ushort v[[A_F16_0:[0-9]+]] +; GFX9: global_load_ushort v[[A_F16_0:[0-9]+]] +; SI: v_mov_b32_e32 v[[A_F32_1:[0-9]+]] +; SI: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_F16_0]] +; SI: v_log_f32_e32 v[[R_F32_0:[0-9]+]], v[[A_F32_0]] +; SI: v_mul_f32_e32 v[[R_F32_1:[0-9]+]], 0x3f317218, v[[R_F32_0]] +; SI: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_1]] +; VIGFX9: v_log_f16_e32 v[[R_F16_0:[0-9]+]], v[[A_F16_0]] +; VIGFX9: v_mul_f16_e32 v[[R_F16_0]], 0x398c, v[[R_F16_0]] +; SI: buffer_store_short v[[R_F16_0]], v{{\[[0-9]+:[0-9]+\]}} +; VI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, v[[R_F16_0]] +; GFX9: global_store_short v{{\[[0-9]+:[0-9]+\]}}, v[[R_F16_0]] +define void @log_f16( + half addrspace(1)* %r, + half addrspace(1)* %a) { +entry: + %a.val = load half, half addrspace(1)* %a + %r.val = call half @llvm.log.f16(half %a.val) + store half %r.val, half addrspace(1)* %r + ret void +} + +; FUNC-LABEL: {{^}}log_v2f16 +; SI: buffer_load_dword v[[A_F16_0:[0-9]+]] +; VI: flat_load_dword v[[A_F16_0:[0-9]+]] +; GFX9: global_load_dword v[[A_F16_0:[0-9]+]] +; SI: v_mov_b32_e32 v[[A_F32_2:[0-9]+]], 0x3f317218 +; VIGFX9: v_mov_b32_e32 v[[A_F32_2:[0-9]+]], 0x398c +; SI: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_0]] +; SI: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_F16_0]] +; SI: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_F16_0]] +; SI: v_log_f32_e32 v[[R_F32_1:[0-9]+]], v[[A_F32_1]] +; SI: v_log_f32_e32 v[[R_F32_0:[0-9]+]], v[[A_F32_0]] +; SI: v_mul_f32_e32 v[[R_F32_6:[0-9]+]], v[[R_F32_1]], v[[A_F32_2]] +; SI: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[R_F32_6]] +; SI: v_mul_f32_e32 v[[R_F32_5:[0-9]+]], v[[R_F32_0]], v[[A_F32_2]] +; SI: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_5]] +; GFX9: v_log_f16_e32 v[[R_F16_2:[0-9]+]], v[[A_F16_0]] +; VIGFX9: v_log_f16_sdwa v[[R_F16_1:[0-9]+]], v[[A_F16_0]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; VI: v_log_f16_e32 v[[R_F16_0:[0-9]+]], v[[A_F16_0]] +; VI: v_mul_f16_sdwa v[[R_F16_2:[0-9]+]], v[[R_F16_1]], v[[A_F32_2]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; GFX9: v_mul_f16_e32 v[[R_F32_3:[0-9]+]], v[[R_F16_2]], v[[A_F32_2]] +; VIGFX9: v_mul_f16_e32 v[[R_F32_2:[0-9]+]], v[[R_F16_0]], v[[A_F32_2]] +; SI: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_0]] +; SI-NOT: v_and_b32_e32 +; SI: v_or_b32_e32 v[[R_F32_5:[0-9]+]], v[[R_F16_1]], v[[R_F16_0]] +; VI-NOT: v_and_b32_e32 +; VI: v_or_b32_e32 v[[R_F32_5:[0-9]+]], v[[R_F16_0]], v[[R_F16_2]] +; GFX9: v_and_b32_e32 v[[R_F32_4:[0-9]+]], 0xffff, v[[R_F32_3]] +; GFX9: v_lshl_or_b32 v[[R_F32_5:[0-9]+]], v[[R_F32_2]], 16, v[[R_F32_4]] +; SI: buffer_store_dword v[[R_F32_5]] +; VI: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v[[R_F32_5]] +; GFX9: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v[[R_F32_5]] +define void @log_v2f16( + <2 x half> addrspace(1)* %r, + <2 x half> addrspace(1)* %a) { +entry: + %a.val = load <2 x half>, <2 x half> addrspace(1)* %a + %r.val = call <2 x half> @llvm.log.v2f16(<2 x half> %a.val) + store <2 x half> %r.val, <2 x half> addrspace(1)* %r + ret void +} diff --git a/llvm/test/CodeGen/AMDGPU/llvm.log.ll b/llvm/test/CodeGen/AMDGPU/llvm.log.ll new file mode 100644 index 0000000..8018bf2 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/llvm.log.ll @@ -0,0 +1,89 @@ +; RUN: llc -march=amdgcn < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=GCN -check-prefix=GFX8 --check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM -check-prefix=FUNC %s + +; FUNC-LABEL: {{^}}test: +; EG: LOG_IEEE +; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} +; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}} +; GCN: v_mul_f32_e32 v{{[0-9]+}}, 0x3f317218, v{{[0-9]+}} +define void @test(float addrspace(1)* %out, float %in) { +entry: + %res = call float @llvm.log.f32(float %in) + store float %res, float addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}testv2: +; EG: LOG_IEEE +; EG: LOG_IEEE +; FIXME: We should be able to merge these packets together on Cayman so we +; have a maximum of 4 instructions. +; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} +; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} +; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}} +; SI: v_mov_b32_e32 v[[R_F32_LOG_CONST:[0-9]+]], 0x3f317218 +; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}} +; GFX8: v_mov_b32_e32 v[[R_F32_LOG_CONST:[0-9]+]], 0x3f317218 +; GCN: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[R_F32_LOG_CONST]] +; GCN: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[R_F32_LOG_CONST]] +define void @testv2(<2 x float> addrspace(1)* %out, <2 x float> %in) { +entry: + %res = call <2 x float> @llvm.log.v2f32(<2 x float> %in) + store <2 x float> %res, <2 x float> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}testv4: +; EG: LOG_IEEE +; EG: LOG_IEEE +; EG: LOG_IEEE +; EG: LOG_IEEE +; FIXME: We should be able to merge these packets together on Cayman so we +; have a maximum of 4 instructions. +; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} +; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} +; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} +; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} +; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}} +; SI: v_mov_b32_e32 v[[R_F32_LOG_CONST:[0-9]+]], 0x3f317218 +; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}} +; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}} +; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}} +; GFX8: v_mov_b32_e32 v[[R_F32_LOG_CONST:[0-9]+]], 0x3f317218 +; GCN: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[R_F32_LOG_CONST]] +; GCN: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[R_F32_LOG_CONST]] +; GCN: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[R_F32_LOG_CONST]] +; GCN: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[R_F32_LOG_CONST]] +define void @testv4(<4 x float> addrspace(1)* %out, <4 x float> %in) { +entry: + %res = call <4 x float> @llvm.log.v4f32(<4 x float> %in) + store <4 x float> %res, <4 x float> addrspace(1)* %out + ret void +} + +declare float @llvm.log.f32(float) readnone +declare <2 x float> @llvm.log.v2f32(<2 x float>) readnone +declare <4 x float> @llvm.log.v4f32(<4 x float>) readnone diff --git a/llvm/test/CodeGen/AMDGPU/llvm.log10.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.log10.f16.ll new file mode 100644 index 0000000..70cac1d --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/llvm.log10.f16.ll @@ -0,0 +1,71 @@ +; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=SIVI -check-prefix=FUNC %s +; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=SIVI -check-prefix=VIGFX9 -check-prefix=FUNC %s +; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 -check-prefix=VIGFX9 -check-prefix=FUNC %s + +declare half @llvm.log10.f16(half %a) +declare <2 x half> @llvm.log10.v2f16(<2 x half> %a) + +; GCN-LABEL: {{^}}log10_f16 +; SI: buffer_load_ushort v[[A_F16_0:[0-9]+]] +; VI: flat_load_ushort v[[A_F16_0:[0-9]+]] +; GFX9: global_load_ushort v[[A_F16_0:[0-9]+]] +; SI: v_mov_b32_e32 v[[A_F32_1:[0-9]+]] +; SI: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_F16_0]] +; SI: v_log_f32_e32 v[[R_F32_0:[0-9]+]], v[[A_F32_0]] +; SI: v_mul_f32_e32 v[[R_F32_1:[0-9]+]], 0x3e9a209a, v[[R_F32_0]] +; SI: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_1]] +; VIGFX9: v_log_f16_e32 v[[R_F16_0:[0-9]+]], v[[A_F16_0]] +; VIGFX9: v_mul_f16_e32 v[[R_F16_0]], 0x34d1, v[[R_F16_0]] +; SI: buffer_store_short v[[R_F16_0]], v{{\[[0-9]+:[0-9]+\]}} +; VI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, v[[R_F16_0]] +; GFX9: global_store_short v{{\[[0-9]+:[0-9]+\]}}, v[[R_F16_0]] +define void @log10_f16( + half addrspace(1)* %r, + half addrspace(1)* %a) { +entry: + %a.val = load half, half addrspace(1)* %a + %r.val = call half @llvm.log10.f16(half %a.val) + store half %r.val, half addrspace(1)* %r + ret void +} + +; GCN-LABEL: {{^}}log10_v2f16 +; SI: buffer_load_dword v[[A_F16_0:[0-9]+]] +; VI: flat_load_dword v[[A_F16_0:[0-9]+]] +; GFX9: global_load_dword v[[A_F16_0:[0-9]+]] +; SI: v_mov_b32_e32 v[[A_F32_2:[0-9]+]], 0x3e9a209a +; VIGFX9: v_mov_b32_e32 v[[A_F32_2:[0-9]+]], 0x34d1 +; SI: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_0]] +; SI: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_F16_0]] +; SI: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_F16_0]] +; SI: v_log_f32_e32 v[[R_F32_1:[0-9]+]], v[[A_F32_1]] +; SI: v_log_f32_e32 v[[R_F32_0:[0-9]+]], v[[A_F32_0]] +; SI: v_mul_f32_e32 v[[R_F32_6:[0-9]+]], v[[R_F32_1]], v[[A_F32_2]] +; SI: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[R_F32_6]] +; SI: v_mul_f32_e32 v[[R_F32_5:[0-9]+]], v[[R_F32_0]], v[[A_F32_2]] +; SI: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_5]] +; GFX9: v_log_f16_e32 v[[R_F16_2:[0-9]+]], v[[A_F16_0]] +; VIGFX9: v_log_f16_sdwa v[[R_F16_1:[0-9]+]], v[[A_F16_0]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; VI: v_log_f16_e32 v[[R_F16_0:[0-9]+]], v[[A_F16_0]] +; VI: v_mul_f16_sdwa v[[R_F16_2:[0-9]+]], v[[R_F16_1]], v[[A_F32_2]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; GFX9: v_mul_f16_e32 v[[R_F32_3:[0-9]+]], v[[R_F16_2]], v[[A_F32_2]] +; VIGFX9: v_mul_f16_e32 v[[R_F32_2:[0-9]+]], v[[R_F16_0]], v[[A_F32_2]] +; SI: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_0]] +; SI-NOT: v_and_b32_e32 +; SI: v_or_b32_e32 v[[R_F32_5:[0-9]+]], v[[R_F16_1]], v[[R_F16_0]] +; VI-NOT: v_and_b32_e32 +; VI: v_or_b32_e32 v[[R_F32_5:[0-9]+]], v[[R_F16_0]], v[[R_F16_2]] +; GFX9: v_and_b32_e32 v[[R_F32_4:[0-9]+]], 0xffff, v[[R_F32_3]] +; GFX9: v_lshl_or_b32 v[[R_F32_5:[0-9]+]], v[[R_F32_2]], 16, v[[R_F32_4]] +; SI: buffer_store_dword v[[R_F32_5]] +; VI: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v[[R_F32_5]] +; GFX9: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v[[R_F32_5]] +define void @log10_v2f16( + <2 x half> addrspace(1)* %r, + <2 x half> addrspace(1)* %a) { +entry: + %a.val = load <2 x half>, <2 x half> addrspace(1)* %a + %r.val = call <2 x half> @llvm.log10.v2f16(<2 x half> %a.val) + store <2 x half> %r.val, <2 x half> addrspace(1)* %r + ret void +} diff --git a/llvm/test/CodeGen/AMDGPU/llvm.log10.ll b/llvm/test/CodeGen/AMDGPU/llvm.log10.ll new file mode 100644 index 0000000..1812f47 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/llvm.log10.ll @@ -0,0 +1,89 @@ +; RUN: llc -march=amdgcn < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=GCN -check-prefix=GFX8 -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM -check-prefix=FUNC %s + +; FUNC-LABEL: {{^}}test: +; EG: LOG_IEEE +; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} +; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}} +; GCN: v_mul_f32_e32 v{{[0-9]+}}, 0x3e9a209a, v{{[0-9]+}} +define void @test(float addrspace(1)* %out, float %in) { +entry: + %res = call float @llvm.log10.f32(float %in) + store float %res, float addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}testv2: +; EG: LOG_IEEE +; EG: LOG_IEEE +; FIXME: We should be able to merge these packets together on Cayman so we +; have a maximum of 4 instructions. +; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} +; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} +; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}} +; SI: v_mov_b32_e32 v[[R_F32_LOG_CONST:[0-9]+]], 0x3e9a209a +; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}} +; GFX8: v_mov_b32_e32 v[[R_F32_LOG_CONST:[0-9]+]], 0x3e9a209a +; GCN: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[R_F32_LOG_CONST]] +; GCN: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[R_F32_LOG_CONST]] +define void @testv2(<2 x float> addrspace(1)* %out, <2 x float> %in) { +entry: + %res = call <2 x float> @llvm.log10.v2f32(<2 x float> %in) + store <2 x float> %res, <2 x float> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}testv4: +; EG: LOG_IEEE +; EG: LOG_IEEE +; EG: LOG_IEEE +; EG: LOG_IEEE +; FIXME: We should be able to merge these packets together on Cayman so we +; have a maximum of 4 instructions. +; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) +; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} +; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} +; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} +; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} +; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}} +; SI: v_mov_b32_e32 v[[R_F32_LOG_CONST:[0-9]+]], 0x3e9a209a +; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}} +; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}} +; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}} +; GFX8: v_mov_b32_e32 v[[R_F32_LOG_CONST:[0-9]+]], 0x3e9a209a +; GCN: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[R_F32_LOG_CONST]] +; GCN: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[R_F32_LOG_CONST]] +; GCN: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[R_F32_LOG_CONST]] +; GCN: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[R_F32_LOG_CONST]] +define void @testv4(<4 x float> addrspace(1)* %out, <4 x float> %in) { +entry: + %res = call <4 x float> @llvm.log10.v4f32(<4 x float> %in) + store <4 x float> %res, <4 x float> addrspace(1)* %out + ret void +} + +declare float @llvm.log10.f32(float) readnone +declare <2 x float> @llvm.log10.v2f32(<2 x float>) readnone +declare <4 x float> @llvm.log10.v4f32(<4 x float>) readnone -- 2.7.4