From ad1cea0ddafe7494e9726623bd08d1814c8cf19e Mon Sep 17 00:00:00 2001 From: Guillaume Chatelet Date: Fri, 6 Sep 2019 15:03:49 +0000 Subject: [PATCH] [Alignment][NFC] Use Align with TargetLowering::setPrefFunctionAlignment Summary: This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: nemanjai, javed.absar, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, s.egerton, pzheng, ychen, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67267 llvm-svn: 371212 --- llvm/include/llvm/CodeGen/TargetLowering.h | 7 +++---- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 3 ++- llvm/lib/Target/BPF/BPFISelLowering.cpp | 4 ++-- llvm/lib/Target/Hexagon/HexagonISelLowering.cpp | 2 +- llvm/lib/Target/Lanai/LanaiISelLowering.cpp | 4 ++-- llvm/lib/Target/MSP430/MSP430ISelLowering.cpp | 2 +- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 4 ++-- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 4 ++-- llvm/lib/Target/SystemZ/SystemZISelLowering.cpp | 2 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 2 +- llvm/lib/Target/XCore/XCoreISelLowering.cpp | 2 +- 11 files changed, 18 insertions(+), 18 deletions(-) diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h index 0c675e4..47edbe0 100644 --- a/llvm/include/llvm/CodeGen/TargetLowering.h +++ b/llvm/include/llvm/CodeGen/TargetLowering.h @@ -2110,10 +2110,9 @@ protected: } /// Set the target's preferred function alignment. This should be set if - /// there is a performance benefit to higher-than-minimum alignment (in - /// log2(bytes)) - void setPrefFunctionLogAlignment(unsigned LogAlign) { - PrefFunctionAlignment = llvm::Align(1ULL << LogAlign); + /// there is a performance benefit to higher-than-minimum alignment + void setPrefFunctionAlignment(llvm::Align Align) { + PrefFunctionAlignment = Align; } /// Set the target's preferred loop alignment. Default alignment is one, it diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index a78f37f..ef535be 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -642,8 +642,9 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM, // Set required alignment. setMinFunctionAlignment(llvm::Align(4)); // Set preferred alignments. - setPrefFunctionLogAlignment(STI.getPrefFunctionLogAlignment()); setPrefLoopAlignment(llvm::Align(1ULL << STI.getPrefLoopLogAlignment())); + setPrefFunctionAlignment( + llvm::Align(1ULL << STI.getPrefFunctionLogAlignment())); // Only change the limit for entries in a jump table if specified by // the sub target, but not at the command line. diff --git a/llvm/lib/Target/BPF/BPFISelLowering.cpp b/llvm/lib/Target/BPF/BPFISelLowering.cpp index 70e0acf..72fe18b 100644 --- a/llvm/lib/Target/BPF/BPFISelLowering.cpp +++ b/llvm/lib/Target/BPF/BPFISelLowering.cpp @@ -132,9 +132,9 @@ BPFTargetLowering::BPFTargetLowering(const TargetMachine &TM, setBooleanContents(ZeroOrOneBooleanContent); - // Function alignments (log2) + // Function alignments setMinFunctionAlignment(llvm::Align(8)); - setPrefFunctionLogAlignment(3); + setPrefFunctionAlignment(llvm::Align(8)); if (BPFExpandMemcpyInOrder) { // LLVM generic code will try to expand memcpy into load/store pairs at this diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp index cea1986..26a178c 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -1236,8 +1236,8 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM, auto &HRI = *Subtarget.getRegisterInfo(); setPrefLoopAlignment(llvm::Align(16)); - setPrefFunctionLogAlignment(4); setMinFunctionAlignment(llvm::Align(4)); + setPrefFunctionAlignment(llvm::Align(16)); setStackPointerRegisterToSaveRestore(HRI.getStackRegister()); setBooleanContents(TargetLoweringBase::UndefinedBooleanContent); setBooleanVectorContents(TargetLoweringBase::UndefinedBooleanContent); diff --git a/llvm/lib/Target/Lanai/LanaiISelLowering.cpp b/llvm/lib/Target/Lanai/LanaiISelLowering.cpp index 4b96853..5cd72da 100644 --- a/llvm/lib/Target/Lanai/LanaiISelLowering.cpp +++ b/llvm/lib/Target/Lanai/LanaiISelLowering.cpp @@ -144,9 +144,9 @@ LanaiTargetLowering::LanaiTargetLowering(const TargetMachine &TM, setTargetDAGCombine(ISD::OR); setTargetDAGCombine(ISD::XOR); - // Function alignments (log2) + // Function alignments setMinFunctionAlignment(llvm::Align(4)); - setPrefFunctionLogAlignment(2); + setPrefFunctionAlignment(llvm::Align(4)); setJumpIsExpensive(true); diff --git a/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp b/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp index 2d0c619..8faa3da 100644 --- a/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp +++ b/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp @@ -328,7 +328,7 @@ MSP430TargetLowering::MSP430TargetLowering(const TargetMachine &TM, // TODO: __mspabi_srall, __mspabi_srlll, __mspabi_sllll setMinFunctionAlignment(llvm::Align(2)); - setPrefFunctionLogAlignment(1); + setPrefFunctionAlignment(llvm::Align(2)); } SDValue MSP430TargetLowering::LowerOperation(SDValue Op, diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 1ed32000..c297b29 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -1182,7 +1182,7 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM, setMinFunctionAlignment(llvm::Align(4)); if (Subtarget.isDarwin()) - setPrefFunctionLogAlignment(4); + setPrefFunctionAlignment(llvm::Align(16)); switch (Subtarget.getDarwinDirective()) { default: break; @@ -1199,8 +1199,8 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM, case PPC::DIR_PWR7: case PPC::DIR_PWR8: case PPC::DIR_PWR9: - setPrefFunctionLogAlignment(4); setPrefLoopAlignment(llvm::Align(16)); + setPrefFunctionAlignment(llvm::Align(16)); break; } diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index ceb931d..371e19c 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -197,10 +197,10 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, setBooleanContents(ZeroOrOneBooleanContent); - // Function alignments (log2). + // Function alignments. const llvm::Align FunctionAlignment(Subtarget.hasStdExtC() ? 2 : 4); setMinFunctionAlignment(FunctionAlignment); - setPrefFunctionLogAlignment(Log2(FunctionAlignment)); + setPrefFunctionAlignment(FunctionAlignment); // Effectively disable jump table generation. setMinimumJumpTableEntries(INT_MAX); diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp index d4d0905..ce15821 100644 --- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp +++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp @@ -122,7 +122,7 @@ SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM, // Instructions are strings of 2-byte aligned 2-byte values. setMinFunctionAlignment(llvm::Align(2)); // For performance reasons we prefer 16-byte alignment. - setPrefFunctionLogAlignment(4); + setPrefFunctionAlignment(llvm::Align(16)); // Handle operations that are handled in a similar way for all types. for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE; diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 9e249ca..5160a31 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -1899,7 +1899,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, // but a conditional move could be stalled by an expensive earlier operation. PredictableSelectIsExpensive = Subtarget.getSchedModel().isOutOfOrder(); EnableExtLdPromotion = true; - setPrefFunctionLogAlignment(4); // 2^4 bytes. + setPrefFunctionAlignment(llvm::Align(16)); verifyIntrinsicTables(); } diff --git a/llvm/lib/Target/XCore/XCoreISelLowering.cpp b/llvm/lib/Target/XCore/XCoreISelLowering.cpp index 88cf9f7..fc6fd40 100644 --- a/llvm/lib/Target/XCore/XCoreISelLowering.cpp +++ b/llvm/lib/Target/XCore/XCoreISelLowering.cpp @@ -172,7 +172,7 @@ XCoreTargetLowering::XCoreTargetLowering(const TargetMachine &TM, setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN); setMinFunctionAlignment(llvm::Align(2)); - setPrefFunctionLogAlignment(2); + setPrefFunctionAlignment(llvm::Align(4)); } bool XCoreTargetLowering::isZExtFree(SDValue Val, EVT VT2) const { -- 2.7.4