From ad1bd2bf658062c6edc5ff1ee1725565a4fc8930 Mon Sep 17 00:00:00 2001 From: Phil Edworthy Date: Tue, 3 May 2022 12:55:57 +0100 Subject: [PATCH] arm64: dts: renesas: Add initial device tree for RZ/V2M EVK Add basic support for RZ/V2M EVK (based on R9A09G011): - memory - External input clock - UART Signed-off-by: Phil Edworthy Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220503115557.53370-13-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/Makefile | 2 ++ arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts | 44 +++++++++++++++++++++++ 2 files changed, 46 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 1530930..e66d76d 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -83,3 +83,5 @@ dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc.dtb dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-smarc.dtb + +dtb-$(CONFIG_ARCH_R9A09G011) += r9a09g011-v2mevk2.dtb diff --git a/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts b/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts new file mode 100644 index 0000000..c207d8c --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/V2M (r9a09g011) Evaluation Kit Board + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r9a09g011.dtsi" + +/ { + model = "RZ/V2M Evaluation Kit 2.0"; + compatible = "renesas,rzv2mevk2", "renesas,r9a09g011"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@58000000 { + device_type = "memory"; + /* + * first 1.25GiB is reserved for ISP Firmware, + * next 128MiB is reserved for secure area. + */ + reg = <0x0 0x58000000 0x0 0x28000000>; + }; + + memory@180000000 { + device_type = "memory"; + reg = <0x1 0x80000000 0x0 0x80000000>; + }; +}; + +&extal_clk { + clock-frequency = <48000000>; +}; + +&uart0 { + status = "okay"; +}; -- 2.7.4