From ad16f3e413545fa87a31f2ae9680b96fd8dd0507 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Fri, 2 Sep 2022 11:49:46 +0100 Subject: [PATCH] [CostModel][X86] Add CostKinds handling for fadd/fsub/fneg ops This was achieved with an updated version of the 'cost-tables vs llvm-mca' script D103695 which I'll update shortly As we're using 'typical' worst case values, not all cost entries come from a single CPU - e.g. the latency/throughput from haswell but the size-latency(uops) from zen1/alderlake-e due to 'double pumping' --- llvm/lib/Target/X86/X86TargetTransformInfo.cpp | 100 ++++-- .../Analysis/CostModel/X86/arith-fp-latency.ll | 388 ++++++++++++++++++--- .../Analysis/CostModel/X86/arith-fp-sizelatency.ll | 344 +++++++++++++++--- .../Analysis/CostModel/X86/intrinsic-cost-kinds.ll | 4 +- 4 files changed, 724 insertions(+), 112 deletions(-) diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp index 52f9413..a1a1b65 100644 --- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp +++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp @@ -350,8 +350,8 @@ InstructionCost X86TTIImpl::getArithmeticInstrCost( { ISD::FDIV, MVT::v4f32, { 39 } }, // divps { ISD::FDIV, MVT::f64, { 32 } }, // divsd { ISD::FDIV, MVT::v2f64, { 69 } }, // divpd - { ISD::FADD, MVT::v2f64, { 2 } }, // addpd - { ISD::FSUB, MVT::v2f64, { 2 } }, // subpd + { ISD::FADD, MVT::v2f64, { 2, 4, 1, 1 } }, // addpd + { ISD::FSUB, MVT::v2f64, { 2, 4, 1, 1 } }, // subpd // v2i64/v4i64 mul is custom lowered as a series of long: // multiplies(3), shifts(3) and adds(2) // slm muldq version throughput is 2 and addq throughput 4 @@ -706,18 +706,22 @@ InstructionCost X86TTIImpl::getArithmeticInstrCost( { ISD::MUL, MVT::v8i64, { 6 } }, // 3*pmuludq/3*shift/2*add { ISD::MUL, MVT::i64, { 1 } }, // Skylake from http://www.agner.org/ - { ISD::FNEG, MVT::v8f64, { 1 } }, // Skylake from http://www.agner.org/ - { ISD::FADD, MVT::v8f64, { 1 } }, // Skylake from http://www.agner.org/ - { ISD::FSUB, MVT::v8f64, { 1 } }, // Skylake from http://www.agner.org/ + { ISD::FNEG, MVT::v8f64, { 1, 1, 1, 2 } }, // Skylake from http://www.agner.org/ + { ISD::FADD, MVT::v8f64, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/ + { ISD::FADD, MVT::v4f64, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/ + { ISD::FSUB, MVT::v8f64, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/ + { ISD::FSUB, MVT::v4f64, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/ { ISD::FMUL, MVT::v8f64, { 1 } }, // Skylake from http://www.agner.org/ { ISD::FDIV, MVT::f64, { 4 } }, // Skylake from http://www.agner.org/ { ISD::FDIV, MVT::v2f64, { 4 } }, // Skylake from http://www.agner.org/ { ISD::FDIV, MVT::v4f64, { 8 } }, // Skylake from http://www.agner.org/ { ISD::FDIV, MVT::v8f64, { 16 } }, // Skylake from http://www.agner.org/ - { ISD::FNEG, MVT::v16f32, { 1 } }, // Skylake from http://www.agner.org/ - { ISD::FADD, MVT::v16f32, { 1 } }, // Skylake from http://www.agner.org/ - { ISD::FSUB, MVT::v16f32, { 1 } }, // Skylake from http://www.agner.org/ + { ISD::FNEG, MVT::v16f32, { 1, 1, 1, 2 } }, // Skylake from http://www.agner.org/ + { ISD::FADD, MVT::v16f32, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/ + { ISD::FADD, MVT::v8f32, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/ + { ISD::FSUB, MVT::v16f32, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/ + { ISD::FSUB, MVT::v8f32, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/ { ISD::FMUL, MVT::v16f32, { 1 } }, // Skylake from http://www.agner.org/ { ISD::FDIV, MVT::f32, { 3 } }, // Skylake from http://www.agner.org/ { ISD::FDIV, MVT::v4f32, { 3 } }, // Skylake from http://www.agner.org/ @@ -887,12 +891,23 @@ InstructionCost X86TTIImpl::getArithmeticInstrCost( { ISD::MUL, MVT::v8i32, { 2 } }, // pmulld (Haswell from agner.org) { ISD::MUL, MVT::v4i64, { 6 } }, // 3*pmuludq/3*shift/2*add - { ISD::FNEG, MVT::v4f64, { 1 } }, // Haswell from http://www.agner.org/ - { ISD::FNEG, MVT::v8f32, { 1 } }, // Haswell from http://www.agner.org/ - { ISD::FADD, MVT::v4f64, { 1 } }, // Haswell from http://www.agner.org/ - { ISD::FADD, MVT::v8f32, { 1 } }, // Haswell from http://www.agner.org/ - { ISD::FSUB, MVT::v4f64, { 1 } }, // Haswell from http://www.agner.org/ - { ISD::FSUB, MVT::v8f32, { 1 } }, // Haswell from http://www.agner.org/ + { ISD::FNEG, MVT::v4f64, { 1, 1, 1, 2 } }, // vxorpd + { ISD::FNEG, MVT::v8f32, { 1, 1, 1, 2 } }, // vxorps + + { ISD::FADD, MVT::f64, { 1, 4, 1, 1 } }, // vaddsd + { ISD::FADD, MVT::f32, { 1, 4, 1, 1 } }, // vaddss + { ISD::FADD, MVT::v2f64, { 1, 4, 1, 1 } }, // vaddpd + { ISD::FADD, MVT::v4f32, { 1, 4, 1, 1 } }, // vaddps + { ISD::FADD, MVT::v4f64, { 1, 4, 1, 2 } }, // vaddpd + { ISD::FADD, MVT::v8f32, { 1, 4, 1, 2 } }, // vaddps + + { ISD::FSUB, MVT::f64, { 1, 4, 1, 1 } }, // vsubsd + { ISD::FSUB, MVT::f32, { 1, 4, 1, 1 } }, // vsubss + { ISD::FSUB, MVT::v2f64, { 1, 4, 1, 1 } }, // vsubpd + { ISD::FSUB, MVT::v4f32, { 1, 4, 1, 1 } }, // vsubps + { ISD::FSUB, MVT::v4f64, { 1, 4, 1, 2 } }, // vsubpd + { ISD::FSUB, MVT::v8f32, { 1, 4, 1, 2 } }, // vsubps + { ISD::FMUL, MVT::f64, { 1 } }, // Haswell from http://www.agner.org/ { ISD::FMUL, MVT::v2f64, { 1 } }, // Haswell from http://www.agner.org/ { ISD::FMUL, MVT::v4f64, { 1 } }, // Haswell from http://www.agner.org/ @@ -966,8 +981,22 @@ InstructionCost X86TTIImpl::getArithmeticInstrCost( { ISD::SRA, MVT::v2i64, { 5 } }, // Shift each lane + blend. { ISD::SRA, MVT::v4i64, { 12 } }, // Shift each lane + blend + split. - { ISD::FNEG, MVT::v4f64, { 2 } }, // BTVER2 from http://www.agner.org/ - { ISD::FNEG, MVT::v8f32, { 2 } }, // BTVER2 from http://www.agner.org/ + { ISD::FNEG, MVT::v4f64, { 2, 2, 1, 2 } }, // BTVER2 from http://www.agner.org/ + { ISD::FNEG, MVT::v8f32, { 2, 2, 1, 2 } }, // BTVER2 from http://www.agner.org/ + + { ISD::FADD, MVT::f64, { 1, 5, 1, 1 } }, // BDVER2 from http://www.agner.org/ + { ISD::FADD, MVT::f32, { 1, 5, 1, 1 } }, // BDVER2 from http://www.agner.org/ + { ISD::FADD, MVT::v2f64, { 1, 5, 1, 1 } }, // BDVER2 from http://www.agner.org/ + { ISD::FADD, MVT::v4f32, { 1, 5, 1, 1 } }, // BDVER2 from http://www.agner.org/ + { ISD::FADD, MVT::v4f64, { 2, 5, 1, 2 } }, // BDVER2 from http://www.agner.org/ + { ISD::FADD, MVT::v8f32, { 2, 5, 1, 2 } }, // BDVER2 from http://www.agner.org/ + + { ISD::FSUB, MVT::f64, { 1, 5, 1, 1 } }, // BDVER2 from http://www.agner.org/ + { ISD::FSUB, MVT::f32, { 1, 5, 1, 1 } }, // BDVER2 from http://www.agner.org/ + { ISD::FSUB, MVT::v2f64, { 1, 5, 1, 1 } }, // BDVER2 from http://www.agner.org/ + { ISD::FSUB, MVT::v4f32, { 1, 5, 1, 1 } }, // BDVER2 from http://www.agner.org/ + { ISD::FSUB, MVT::v4f64, { 2, 5, 1, 2 } }, // BDVER2 from http://www.agner.org/ + { ISD::FSUB, MVT::v8f32, { 2, 5, 1, 2 } }, // BDVER2 from http://www.agner.org/ { ISD::FMUL, MVT::f64, { 2 } }, // BTVER2 from http://www.agner.org/ { ISD::FMUL, MVT::v2f64, { 2 } }, // BTVER2 from http://www.agner.org/ @@ -1078,16 +1107,18 @@ InstructionCost X86TTIImpl::getArithmeticInstrCost( { ISD::FDIV, MVT::f64, { 38 } }, // Pentium IV from http://www.agner.org/ { ISD::FDIV, MVT::v2f64, { 69 } }, // Pentium IV from http://www.agner.org/ - { ISD::FNEG, MVT::f32, { 1 } }, // Pentium IV from http://www.agner.org/ - { ISD::FNEG, MVT::f64, { 1 } }, // Pentium IV from http://www.agner.org/ - { ISD::FNEG, MVT::v4f32, { 1 } }, // Pentium IV from http://www.agner.org/ - { ISD::FNEG, MVT::v2f64, { 1 } }, // Pentium IV from http://www.agner.org/ + { ISD::FNEG, MVT::f32, { 1, 1, 1, 1 } }, // Pentium IV from http://www.agner.org/ + { ISD::FNEG, MVT::f64, { 1, 1, 1, 1 } }, // Pentium IV from http://www.agner.org/ + { ISD::FNEG, MVT::v4f32, { 1, 1, 1, 1 } }, // Pentium IV from http://www.agner.org/ + { ISD::FNEG, MVT::v2f64, { 1, 1, 1, 1 } }, // Pentium IV from http://www.agner.org/ - { ISD::FADD, MVT::f32, { 2 } }, // Pentium IV from http://www.agner.org/ - { ISD::FADD, MVT::f64, { 2 } }, // Pentium IV from http://www.agner.org/ + { ISD::FADD, MVT::f32, { 2, 3, 1, 1 } }, // Pentium IV from http://www.agner.org/ + { ISD::FADD, MVT::f64, { 2, 3, 1, 1 } }, // Pentium IV from http://www.agner.org/ + { ISD::FADD, MVT::v2f64, { 2, 3, 1, 1 } }, // Pentium IV from http://www.agner.org/ - { ISD::FSUB, MVT::f32, { 2 } }, // Pentium IV from http://www.agner.org/ - { ISD::FSUB, MVT::f64, { 2 } }, // Pentium IV from http://www.agner.org/ + { ISD::FSUB, MVT::f32, { 2, 3, 1, 1 } }, // Pentium IV from http://www.agner.org/ + { ISD::FSUB, MVT::f64, { 2, 3, 1, 1 } }, // Pentium IV from http://www.agner.org/ + { ISD::FSUB, MVT::v2f64, { 2, 3, 1, 1 } }, // Pentium IV from http://www.agner.org/ }; if (ST->hasSSE2()) @@ -1099,14 +1130,14 @@ InstructionCost X86TTIImpl::getArithmeticInstrCost( { ISD::FDIV, MVT::f32, { 17 } }, // Pentium III from http://www.agner.org/ { ISD::FDIV, MVT::v4f32, { 34 } }, // Pentium III from http://www.agner.org/ - { ISD::FNEG, MVT::f32, { 2 } }, // Pentium III from http://www.agner.org/ - { ISD::FNEG, MVT::v4f32, { 2 } }, // Pentium III from http://www.agner.org/ + { ISD::FNEG, MVT::f32, { 2, 2, 1, 2 } }, // Pentium III from http://www.agner.org/ + { ISD::FNEG, MVT::v4f32, { 2, 2, 1, 2 } }, // Pentium III from http://www.agner.org/ - { ISD::FADD, MVT::f32, { 1 } }, // Pentium III from http://www.agner.org/ - { ISD::FADD, MVT::v4f32, { 2 } }, // Pentium III from http://www.agner.org/ + { ISD::FADD, MVT::f32, { 1, 3, 1, 1 } }, // Pentium III from http://www.agner.org/ + { ISD::FADD, MVT::v4f32, { 2, 3, 1, 1 } }, // Pentium III from http://www.agner.org/ - { ISD::FSUB, MVT::f32, { 1 } }, // Pentium III from http://www.agner.org/ - { ISD::FSUB, MVT::v4f32, { 2 } }, // Pentium III from http://www.agner.org/ + { ISD::FSUB, MVT::f32, { 1, 3, 1, 1 } }, // Pentium III from http://www.agner.org/ + { ISD::FSUB, MVT::v4f32, { 2, 3, 1, 1 } }, // Pentium III from http://www.agner.org/ }; if (ST->hasSSE1()) @@ -1133,6 +1164,15 @@ InstructionCost X86TTIImpl::getArithmeticInstrCost( { ISD::SUB, MVT::i8, { 1 } }, // Pentium III from http://www.agner.org/ { ISD::SUB, MVT::i16, { 1 } }, // Pentium III from http://www.agner.org/ { ISD::SUB, MVT::i32, { 1 } }, // Pentium III from http://www.agner.org/ + + { ISD::FNEG, MVT::f32, { 2, 2, 1, 3 } }, // (x87) + { ISD::FNEG, MVT::f64, { 2, 2, 1, 3 } }, // (x87) + + { ISD::FADD, MVT::f32, { 2, 3, 1, 1 } }, // (x87) + { ISD::FADD, MVT::f64, { 2, 3, 1, 1 } }, // (x87) + + { ISD::FSUB, MVT::f32, { 2, 3, 1, 1 } }, // (x87) + { ISD::FSUB, MVT::f64, { 2, 3, 1, 1 } }, // (x87) }; if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, LT.second)) diff --git a/llvm/test/Analysis/CostModel/X86/arith-fp-latency.ll b/llvm/test/Analysis/CostModel/X86/arith-fp-latency.ll index 4612836..3161649 100644 --- a/llvm/test/Analysis/CostModel/X86/arith-fp-latency.ll +++ b/llvm/test/Analysis/CostModel/X86/arith-fp-latency.ll @@ -12,16 +12,93 @@ ; RUN: opt < %s -enable-no-nans-fp-math -passes="print" 2>&1 -disable-output -cost-kind=latency -mtriple=x86_64-- -mcpu=btver2 | FileCheck %s --check-prefixes=CHECK,AVX,AVX1 define i32 @fadd(i32 %arg) { -; CHECK-LABEL: 'fadd' -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %F32 = fadd float undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4F32 = fadd <4 x float> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V8F32 = fadd <8 x float> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V16F32 = fadd <16 x float> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %F64 = fadd double undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2F64 = fadd <2 x double> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4F64 = fadd <4 x double> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V8F64 = fadd <8 x double> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; SSE1-LABEL: 'fadd' +; SSE1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %F32 = fadd float undef, undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4F32 = fadd <4 x float> undef, undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8F32 = fadd <8 x float> undef, undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V16F32 = fadd <16 x float> undef, undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %F64 = fadd double undef, undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2F64 = fadd <2 x double> undef, undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V4F64 = fadd <4 x double> undef, undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V8F64 = fadd <8 x double> undef, undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; +; SSE2-LABEL: 'fadd' +; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %F32 = fadd float undef, undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4F32 = fadd <4 x float> undef, undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8F32 = fadd <8 x float> undef, undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V16F32 = fadd <16 x float> undef, undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %F64 = fadd double undef, undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2F64 = fadd <2 x double> undef, undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4F64 = fadd <4 x double> undef, undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V8F64 = fadd <8 x double> undef, undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; +; SSE42-LABEL: 'fadd' +; SSE42-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %F32 = fadd float undef, undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4F32 = fadd <4 x float> undef, undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8F32 = fadd <8 x float> undef, undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V16F32 = fadd <16 x float> undef, undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %F64 = fadd double undef, undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2F64 = fadd <2 x double> undef, undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4F64 = fadd <4 x double> undef, undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V8F64 = fadd <8 x double> undef, undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; +; AVX1-LABEL: 'fadd' +; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %F32 = fadd float undef, undef +; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4F32 = fadd <4 x float> undef, undef +; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V8F32 = fadd <8 x float> undef, undef +; AVX1-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V16F32 = fadd <16 x float> undef, undef +; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %F64 = fadd double undef, undef +; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2F64 = fadd <2 x double> undef, undef +; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4F64 = fadd <4 x double> undef, undef +; AVX1-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V8F64 = fadd <8 x double> undef, undef +; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; +; AVX2-LABEL: 'fadd' +; AVX2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %F32 = fadd float undef, undef +; AVX2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4F32 = fadd <4 x float> undef, undef +; AVX2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8F32 = fadd <8 x float> undef, undef +; AVX2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16F32 = fadd <16 x float> undef, undef +; AVX2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %F64 = fadd double undef, undef +; AVX2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2F64 = fadd <2 x double> undef, undef +; AVX2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4F64 = fadd <4 x double> undef, undef +; AVX2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V8F64 = fadd <8 x double> undef, undef +; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; +; AVX512-LABEL: 'fadd' +; AVX512-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %F32 = fadd float undef, undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4F32 = fadd <4 x float> undef, undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8F32 = fadd <8 x float> undef, undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16F32 = fadd <16 x float> undef, undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %F64 = fadd double undef, undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2F64 = fadd <2 x double> undef, undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4F64 = fadd <4 x double> undef, undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8F64 = fadd <8 x double> undef, undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; +; SLM-LABEL: 'fadd' +; SLM-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %F32 = fadd float undef, undef +; SLM-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4F32 = fadd <4 x float> undef, undef +; SLM-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8F32 = fadd <8 x float> undef, undef +; SLM-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V16F32 = fadd <16 x float> undef, undef +; SLM-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %F64 = fadd double undef, undef +; SLM-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2F64 = fadd <2 x double> undef, undef +; SLM-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V4F64 = fadd <4 x double> undef, undef +; SLM-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8F64 = fadd <8 x double> undef, undef +; SLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; +; GLM-LABEL: 'fadd' +; GLM-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %F32 = fadd float undef, undef +; GLM-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4F32 = fadd <4 x float> undef, undef +; GLM-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8F32 = fadd <8 x float> undef, undef +; GLM-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V16F32 = fadd <16 x float> undef, undef +; GLM-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %F64 = fadd double undef, undef +; GLM-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2F64 = fadd <2 x double> undef, undef +; GLM-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4F64 = fadd <4 x double> undef, undef +; GLM-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V8F64 = fadd <8 x double> undef, undef +; GLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef ; %F32 = fadd float undef, undef %V4F32 = fadd <4 x float> undef, undef @@ -37,16 +114,93 @@ define i32 @fadd(i32 %arg) { } define i32 @fsub(i32 %arg) { -; CHECK-LABEL: 'fsub' -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %F32 = fsub float undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4F32 = fsub <4 x float> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V8F32 = fsub <8 x float> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V16F32 = fsub <16 x float> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %F64 = fsub double undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2F64 = fsub <2 x double> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4F64 = fsub <4 x double> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V8F64 = fsub <8 x double> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; SSE1-LABEL: 'fsub' +; SSE1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %F32 = fsub float undef, undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4F32 = fsub <4 x float> undef, undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8F32 = fsub <8 x float> undef, undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V16F32 = fsub <16 x float> undef, undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %F64 = fsub double undef, undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2F64 = fsub <2 x double> undef, undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V4F64 = fsub <4 x double> undef, undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V8F64 = fsub <8 x double> undef, undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; +; SSE2-LABEL: 'fsub' +; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %F32 = fsub float undef, undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4F32 = fsub <4 x float> undef, undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8F32 = fsub <8 x float> undef, undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V16F32 = fsub <16 x float> undef, undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %F64 = fsub double undef, undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2F64 = fsub <2 x double> undef, undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4F64 = fsub <4 x double> undef, undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V8F64 = fsub <8 x double> undef, undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; +; SSE42-LABEL: 'fsub' +; SSE42-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %F32 = fsub float undef, undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4F32 = fsub <4 x float> undef, undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8F32 = fsub <8 x float> undef, undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V16F32 = fsub <16 x float> undef, undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %F64 = fsub double undef, undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2F64 = fsub <2 x double> undef, undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4F64 = fsub <4 x double> undef, undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V8F64 = fsub <8 x double> undef, undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; +; AVX1-LABEL: 'fsub' +; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %F32 = fsub float undef, undef +; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4F32 = fsub <4 x float> undef, undef +; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V8F32 = fsub <8 x float> undef, undef +; AVX1-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V16F32 = fsub <16 x float> undef, undef +; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %F64 = fsub double undef, undef +; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2F64 = fsub <2 x double> undef, undef +; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4F64 = fsub <4 x double> undef, undef +; AVX1-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V8F64 = fsub <8 x double> undef, undef +; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; +; AVX2-LABEL: 'fsub' +; AVX2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %F32 = fsub float undef, undef +; AVX2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4F32 = fsub <4 x float> undef, undef +; AVX2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8F32 = fsub <8 x float> undef, undef +; AVX2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16F32 = fsub <16 x float> undef, undef +; AVX2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %F64 = fsub double undef, undef +; AVX2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2F64 = fsub <2 x double> undef, undef +; AVX2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4F64 = fsub <4 x double> undef, undef +; AVX2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V8F64 = fsub <8 x double> undef, undef +; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; +; AVX512-LABEL: 'fsub' +; AVX512-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %F32 = fsub float undef, undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4F32 = fsub <4 x float> undef, undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8F32 = fsub <8 x float> undef, undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16F32 = fsub <16 x float> undef, undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %F64 = fsub double undef, undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2F64 = fsub <2 x double> undef, undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4F64 = fsub <4 x double> undef, undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8F64 = fsub <8 x double> undef, undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; +; SLM-LABEL: 'fsub' +; SLM-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %F32 = fsub float undef, undef +; SLM-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4F32 = fsub <4 x float> undef, undef +; SLM-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8F32 = fsub <8 x float> undef, undef +; SLM-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V16F32 = fsub <16 x float> undef, undef +; SLM-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %F64 = fsub double undef, undef +; SLM-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2F64 = fsub <2 x double> undef, undef +; SLM-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V4F64 = fsub <4 x double> undef, undef +; SLM-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8F64 = fsub <8 x double> undef, undef +; SLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; +; GLM-LABEL: 'fsub' +; GLM-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %F32 = fsub float undef, undef +; GLM-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4F32 = fsub <4 x float> undef, undef +; GLM-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8F32 = fsub <8 x float> undef, undef +; GLM-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V16F32 = fsub <16 x float> undef, undef +; GLM-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %F64 = fsub double undef, undef +; GLM-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2F64 = fsub <2 x double> undef, undef +; GLM-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4F64 = fsub <4 x double> undef, undef +; GLM-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V8F64 = fsub <8 x double> undef, undef +; GLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef ; %F32 = fsub float undef, undef %V4F32 = fsub <4 x float> undef, undef @@ -62,16 +216,93 @@ define i32 @fsub(i32 %arg) { } define i32 @fneg_idiom(i32 %arg) { -; CHECK-LABEL: 'fneg_idiom' -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %F32 = fsub float -0.000000e+00, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4F32 = fsub <4 x float> , undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V8F32 = fsub <8 x float> , undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V16F32 = fsub <16 x float> , undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %F64 = fsub double -0.000000e+00, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2F64 = fsub <2 x double> , undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4F64 = fsub <4 x double> , undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V8F64 = fsub <8 x double> , undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; SSE1-LABEL: 'fneg_idiom' +; SSE1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %F32 = fsub float -0.000000e+00, undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4F32 = fsub <4 x float> , undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8F32 = fsub <8 x float> , undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V16F32 = fsub <16 x float> , undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %F64 = fsub double -0.000000e+00, undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2F64 = fsub <2 x double> , undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V4F64 = fsub <4 x double> , undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V8F64 = fsub <8 x double> , undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; +; SSE2-LABEL: 'fneg_idiom' +; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %F32 = fsub float -0.000000e+00, undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4F32 = fsub <4 x float> , undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8F32 = fsub <8 x float> , undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V16F32 = fsub <16 x float> , undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %F64 = fsub double -0.000000e+00, undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2F64 = fsub <2 x double> , undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4F64 = fsub <4 x double> , undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V8F64 = fsub <8 x double> , undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; +; SSE42-LABEL: 'fneg_idiom' +; SSE42-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %F32 = fsub float -0.000000e+00, undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4F32 = fsub <4 x float> , undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8F32 = fsub <8 x float> , undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V16F32 = fsub <16 x float> , undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %F64 = fsub double -0.000000e+00, undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2F64 = fsub <2 x double> , undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4F64 = fsub <4 x double> , undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V8F64 = fsub <8 x double> , undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; +; AVX1-LABEL: 'fneg_idiom' +; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %F32 = fsub float -0.000000e+00, undef +; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4F32 = fsub <4 x float> , undef +; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V8F32 = fsub <8 x float> , undef +; AVX1-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V16F32 = fsub <16 x float> , undef +; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %F64 = fsub double -0.000000e+00, undef +; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2F64 = fsub <2 x double> , undef +; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4F64 = fsub <4 x double> , undef +; AVX1-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V8F64 = fsub <8 x double> , undef +; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; +; AVX2-LABEL: 'fneg_idiom' +; AVX2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %F32 = fsub float -0.000000e+00, undef +; AVX2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4F32 = fsub <4 x float> , undef +; AVX2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8F32 = fsub <8 x float> , undef +; AVX2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16F32 = fsub <16 x float> , undef +; AVX2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %F64 = fsub double -0.000000e+00, undef +; AVX2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2F64 = fsub <2 x double> , undef +; AVX2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4F64 = fsub <4 x double> , undef +; AVX2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V8F64 = fsub <8 x double> , undef +; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; +; AVX512-LABEL: 'fneg_idiom' +; AVX512-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %F32 = fsub float -0.000000e+00, undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4F32 = fsub <4 x float> , undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8F32 = fsub <8 x float> , undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16F32 = fsub <16 x float> , undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %F64 = fsub double -0.000000e+00, undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2F64 = fsub <2 x double> , undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4F64 = fsub <4 x double> , undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8F64 = fsub <8 x double> , undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; +; SLM-LABEL: 'fneg_idiom' +; SLM-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %F32 = fsub float -0.000000e+00, undef +; SLM-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4F32 = fsub <4 x float> , undef +; SLM-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8F32 = fsub <8 x float> , undef +; SLM-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V16F32 = fsub <16 x float> , undef +; SLM-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %F64 = fsub double -0.000000e+00, undef +; SLM-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2F64 = fsub <2 x double> , undef +; SLM-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V4F64 = fsub <4 x double> , undef +; SLM-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8F64 = fsub <8 x double> , undef +; SLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; +; GLM-LABEL: 'fneg_idiom' +; GLM-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %F32 = fsub float -0.000000e+00, undef +; GLM-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4F32 = fsub <4 x float> , undef +; GLM-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8F32 = fsub <8 x float> , undef +; GLM-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V16F32 = fsub <16 x float> , undef +; GLM-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %F64 = fsub double -0.000000e+00, undef +; GLM-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2F64 = fsub <2 x double> , undef +; GLM-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4F64 = fsub <4 x double> , undef +; GLM-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V8F64 = fsub <8 x double> , undef +; GLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef ; %F32 = fsub float -0.0, undef %V4F32 = fsub <4 x float> , undef @@ -87,16 +318,93 @@ define i32 @fneg_idiom(i32 %arg) { } define i32 @fneg(i32 %arg) { -; CHECK-LABEL: 'fneg' -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %F32 = fneg float undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4F32 = fneg <4 x float> undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V8F32 = fneg <8 x float> undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V16F32 = fneg <16 x float> undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %F64 = fneg double undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2F64 = fneg <2 x double> undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4F64 = fneg <4 x double> undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V8F64 = fneg <8 x double> undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; SSE1-LABEL: 'fneg' +; SSE1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %F32 = fneg float undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4F32 = fneg <4 x float> undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8F32 = fneg <8 x float> undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16F32 = fneg <16 x float> undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %F64 = fneg double undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2F64 = fneg <2 x double> undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V4F64 = fneg <4 x double> undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8F64 = fneg <8 x double> undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; +; SSE2-LABEL: 'fneg' +; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = fneg float undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F32 = fneg <4 x float> undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8F32 = fneg <8 x float> undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16F32 = fneg <16 x float> undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = fneg double undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2F64 = fneg <2 x double> undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4F64 = fneg <4 x double> undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8F64 = fneg <8 x double> undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; +; SSE42-LABEL: 'fneg' +; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = fneg float undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F32 = fneg <4 x float> undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8F32 = fneg <8 x float> undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16F32 = fneg <16 x float> undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = fneg double undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2F64 = fneg <2 x double> undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4F64 = fneg <4 x double> undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8F64 = fneg <8 x double> undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; +; AVX1-LABEL: 'fneg' +; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = fneg float undef +; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F32 = fneg <4 x float> undef +; AVX1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8F32 = fneg <8 x float> undef +; AVX1-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16F32 = fneg <16 x float> undef +; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = fneg double undef +; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2F64 = fneg <2 x double> undef +; AVX1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4F64 = fneg <4 x double> undef +; AVX1-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8F64 = fneg <8 x double> undef +; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; +; AVX2-LABEL: 'fneg' +; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = fneg float undef +; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F32 = fneg <4 x float> undef +; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8F32 = fneg <8 x float> undef +; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16F32 = fneg <16 x float> undef +; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = fneg double undef +; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2F64 = fneg <2 x double> undef +; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F64 = fneg <4 x double> undef +; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8F64 = fneg <8 x double> undef +; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; +; AVX512-LABEL: 'fneg' +; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = fneg float undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F32 = fneg <4 x float> undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8F32 = fneg <8 x float> undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16F32 = fneg <16 x float> undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = fneg double undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2F64 = fneg <2 x double> undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F64 = fneg <4 x double> undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8F64 = fneg <8 x double> undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; +; SLM-LABEL: 'fneg' +; SLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = fneg float undef +; SLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F32 = fneg <4 x float> undef +; SLM-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8F32 = fneg <8 x float> undef +; SLM-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16F32 = fneg <16 x float> undef +; SLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = fneg double undef +; SLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2F64 = fneg <2 x double> undef +; SLM-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4F64 = fneg <4 x double> undef +; SLM-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8F64 = fneg <8 x double> undef +; SLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; +; GLM-LABEL: 'fneg' +; GLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = fneg float undef +; GLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F32 = fneg <4 x float> undef +; GLM-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8F32 = fneg <8 x float> undef +; GLM-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16F32 = fneg <16 x float> undef +; GLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = fneg double undef +; GLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2F64 = fneg <2 x double> undef +; GLM-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4F64 = fneg <4 x double> undef +; GLM-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8F64 = fneg <8 x double> undef +; GLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef ; %F32 = fneg float undef %V4F32 = fneg <4 x float> undef diff --git a/llvm/test/Analysis/CostModel/X86/arith-fp-sizelatency.ll b/llvm/test/Analysis/CostModel/X86/arith-fp-sizelatency.ll index bbeff8a..ca3074c 100644 --- a/llvm/test/Analysis/CostModel/X86/arith-fp-sizelatency.ll +++ b/llvm/test/Analysis/CostModel/X86/arith-fp-sizelatency.ll @@ -12,16 +12,82 @@ ; RUN: opt < %s -enable-no-nans-fp-math -passes="print" 2>&1 -disable-output -cost-kind=size-latency -mtriple=x86_64-- -mcpu=btver2 | FileCheck %s --check-prefixes=CHECK,AVX,AVX1 define i32 @fadd(i32 %arg) { -; CHECK-LABEL: 'fadd' -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = fadd float undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F32 = fadd <4 x float> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8F32 = fadd <8 x float> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16F32 = fadd <16 x float> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = fadd double undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2F64 = fadd <2 x double> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F64 = fadd <4 x double> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8F64 = fadd <8 x double> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; SSE1-LABEL: 'fadd' +; SSE1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = fadd float undef, undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F32 = fadd <4 x float> undef, undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8F32 = fadd <8 x float> undef, undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16F32 = fadd <16 x float> undef, undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = fadd double undef, undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2F64 = fadd <2 x double> undef, undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4F64 = fadd <4 x double> undef, undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V8F64 = fadd <8 x double> undef, undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; +; SSE2-LABEL: 'fadd' +; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = fadd float undef, undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F32 = fadd <4 x float> undef, undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8F32 = fadd <8 x float> undef, undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16F32 = fadd <16 x float> undef, undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = fadd double undef, undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2F64 = fadd <2 x double> undef, undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4F64 = fadd <4 x double> undef, undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8F64 = fadd <8 x double> undef, undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; +; SSE42-LABEL: 'fadd' +; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = fadd float undef, undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F32 = fadd <4 x float> undef, undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8F32 = fadd <8 x float> undef, undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16F32 = fadd <16 x float> undef, undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = fadd double undef, undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2F64 = fadd <2 x double> undef, undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4F64 = fadd <4 x double> undef, undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8F64 = fadd <8 x double> undef, undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; +; AVX-LABEL: 'fadd' +; AVX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = fadd float undef, undef +; AVX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F32 = fadd <4 x float> undef, undef +; AVX-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8F32 = fadd <8 x float> undef, undef +; AVX-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16F32 = fadd <16 x float> undef, undef +; AVX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = fadd double undef, undef +; AVX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2F64 = fadd <2 x double> undef, undef +; AVX-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4F64 = fadd <4 x double> undef, undef +; AVX-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8F64 = fadd <8 x double> undef, undef +; AVX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; +; AVX512-LABEL: 'fadd' +; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = fadd float undef, undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F32 = fadd <4 x float> undef, undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8F32 = fadd <8 x float> undef, undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16F32 = fadd <16 x float> undef, undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = fadd double undef, undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2F64 = fadd <2 x double> undef, undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F64 = fadd <4 x double> undef, undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8F64 = fadd <8 x double> undef, undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; +; SLM-LABEL: 'fadd' +; SLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = fadd float undef, undef +; SLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F32 = fadd <4 x float> undef, undef +; SLM-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8F32 = fadd <8 x float> undef, undef +; SLM-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16F32 = fadd <16 x float> undef, undef +; SLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = fadd double undef, undef +; SLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2F64 = fadd <2 x double> undef, undef +; SLM-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4F64 = fadd <4 x double> undef, undef +; SLM-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8F64 = fadd <8 x double> undef, undef +; SLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; +; GLM-LABEL: 'fadd' +; GLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = fadd float undef, undef +; GLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F32 = fadd <4 x float> undef, undef +; GLM-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8F32 = fadd <8 x float> undef, undef +; GLM-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16F32 = fadd <16 x float> undef, undef +; GLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = fadd double undef, undef +; GLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2F64 = fadd <2 x double> undef, undef +; GLM-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4F64 = fadd <4 x double> undef, undef +; GLM-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8F64 = fadd <8 x double> undef, undef +; GLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef ; %F32 = fadd float undef, undef %V4F32 = fadd <4 x float> undef, undef @@ -37,16 +103,82 @@ define i32 @fadd(i32 %arg) { } define i32 @fsub(i32 %arg) { -; CHECK-LABEL: 'fsub' -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = fsub float undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F32 = fsub <4 x float> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8F32 = fsub <8 x float> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16F32 = fsub <16 x float> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = fsub double undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2F64 = fsub <2 x double> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F64 = fsub <4 x double> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8F64 = fsub <8 x double> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; SSE1-LABEL: 'fsub' +; SSE1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = fsub float undef, undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F32 = fsub <4 x float> undef, undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8F32 = fsub <8 x float> undef, undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16F32 = fsub <16 x float> undef, undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = fsub double undef, undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2F64 = fsub <2 x double> undef, undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4F64 = fsub <4 x double> undef, undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V8F64 = fsub <8 x double> undef, undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; +; SSE2-LABEL: 'fsub' +; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = fsub float undef, undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F32 = fsub <4 x float> undef, undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8F32 = fsub <8 x float> undef, undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16F32 = fsub <16 x float> undef, undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = fsub double undef, undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2F64 = fsub <2 x double> undef, undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4F64 = fsub <4 x double> undef, undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8F64 = fsub <8 x double> undef, undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; +; SSE42-LABEL: 'fsub' +; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = fsub float undef, undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F32 = fsub <4 x float> undef, undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8F32 = fsub <8 x float> undef, undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16F32 = fsub <16 x float> undef, undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = fsub double undef, undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2F64 = fsub <2 x double> undef, undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4F64 = fsub <4 x double> undef, undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8F64 = fsub <8 x double> undef, undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; +; AVX-LABEL: 'fsub' +; AVX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = fsub float undef, undef +; AVX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F32 = fsub <4 x float> undef, undef +; AVX-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8F32 = fsub <8 x float> undef, undef +; AVX-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16F32 = fsub <16 x float> undef, undef +; AVX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = fsub double undef, undef +; AVX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2F64 = fsub <2 x double> undef, undef +; AVX-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4F64 = fsub <4 x double> undef, undef +; AVX-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8F64 = fsub <8 x double> undef, undef +; AVX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; +; AVX512-LABEL: 'fsub' +; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = fsub float undef, undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F32 = fsub <4 x float> undef, undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8F32 = fsub <8 x float> undef, undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16F32 = fsub <16 x float> undef, undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = fsub double undef, undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2F64 = fsub <2 x double> undef, undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F64 = fsub <4 x double> undef, undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8F64 = fsub <8 x double> undef, undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; +; SLM-LABEL: 'fsub' +; SLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = fsub float undef, undef +; SLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F32 = fsub <4 x float> undef, undef +; SLM-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8F32 = fsub <8 x float> undef, undef +; SLM-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16F32 = fsub <16 x float> undef, undef +; SLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = fsub double undef, undef +; SLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2F64 = fsub <2 x double> undef, undef +; SLM-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4F64 = fsub <4 x double> undef, undef +; SLM-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8F64 = fsub <8 x double> undef, undef +; SLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; +; GLM-LABEL: 'fsub' +; GLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = fsub float undef, undef +; GLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F32 = fsub <4 x float> undef, undef +; GLM-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8F32 = fsub <8 x float> undef, undef +; GLM-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16F32 = fsub <16 x float> undef, undef +; GLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = fsub double undef, undef +; GLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2F64 = fsub <2 x double> undef, undef +; GLM-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4F64 = fsub <4 x double> undef, undef +; GLM-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8F64 = fsub <8 x double> undef, undef +; GLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef ; %F32 = fsub float undef, undef %V4F32 = fsub <4 x float> undef, undef @@ -62,16 +194,82 @@ define i32 @fsub(i32 %arg) { } define i32 @fneg_idiom(i32 %arg) { -; CHECK-LABEL: 'fneg_idiom' -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = fsub float -0.000000e+00, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F32 = fsub <4 x float> , undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8F32 = fsub <8 x float> , undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16F32 = fsub <16 x float> , undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = fsub double -0.000000e+00, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2F64 = fsub <2 x double> , undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F64 = fsub <4 x double> , undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8F64 = fsub <8 x double> , undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; SSE1-LABEL: 'fneg_idiom' +; SSE1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = fsub float -0.000000e+00, undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F32 = fsub <4 x float> , undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8F32 = fsub <8 x float> , undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16F32 = fsub <16 x float> , undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = fsub double -0.000000e+00, undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2F64 = fsub <2 x double> , undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4F64 = fsub <4 x double> , undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V8F64 = fsub <8 x double> , undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; +; SSE2-LABEL: 'fneg_idiom' +; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = fsub float -0.000000e+00, undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F32 = fsub <4 x float> , undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8F32 = fsub <8 x float> , undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16F32 = fsub <16 x float> , undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = fsub double -0.000000e+00, undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2F64 = fsub <2 x double> , undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4F64 = fsub <4 x double> , undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8F64 = fsub <8 x double> , undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; +; SSE42-LABEL: 'fneg_idiom' +; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = fsub float -0.000000e+00, undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F32 = fsub <4 x float> , undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8F32 = fsub <8 x float> , undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16F32 = fsub <16 x float> , undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = fsub double -0.000000e+00, undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2F64 = fsub <2 x double> , undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4F64 = fsub <4 x double> , undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8F64 = fsub <8 x double> , undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; +; AVX-LABEL: 'fneg_idiom' +; AVX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = fsub float -0.000000e+00, undef +; AVX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F32 = fsub <4 x float> , undef +; AVX-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8F32 = fsub <8 x float> , undef +; AVX-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16F32 = fsub <16 x float> , undef +; AVX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = fsub double -0.000000e+00, undef +; AVX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2F64 = fsub <2 x double> , undef +; AVX-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4F64 = fsub <4 x double> , undef +; AVX-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8F64 = fsub <8 x double> , undef +; AVX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; +; AVX512-LABEL: 'fneg_idiom' +; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = fsub float -0.000000e+00, undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F32 = fsub <4 x float> , undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8F32 = fsub <8 x float> , undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16F32 = fsub <16 x float> , undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = fsub double -0.000000e+00, undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2F64 = fsub <2 x double> , undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F64 = fsub <4 x double> , undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8F64 = fsub <8 x double> , undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; +; SLM-LABEL: 'fneg_idiom' +; SLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = fsub float -0.000000e+00, undef +; SLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F32 = fsub <4 x float> , undef +; SLM-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8F32 = fsub <8 x float> , undef +; SLM-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16F32 = fsub <16 x float> , undef +; SLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = fsub double -0.000000e+00, undef +; SLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2F64 = fsub <2 x double> , undef +; SLM-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4F64 = fsub <4 x double> , undef +; SLM-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8F64 = fsub <8 x double> , undef +; SLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; +; GLM-LABEL: 'fneg_idiom' +; GLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = fsub float -0.000000e+00, undef +; GLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F32 = fsub <4 x float> , undef +; GLM-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8F32 = fsub <8 x float> , undef +; GLM-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16F32 = fsub <16 x float> , undef +; GLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = fsub double -0.000000e+00, undef +; GLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2F64 = fsub <2 x double> , undef +; GLM-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4F64 = fsub <4 x double> , undef +; GLM-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8F64 = fsub <8 x double> , undef +; GLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef ; %F32 = fsub float -0.0, undef %V4F32 = fsub <4 x float> , undef @@ -87,16 +285,82 @@ define i32 @fneg_idiom(i32 %arg) { } define i32 @fneg(i32 %arg) { -; CHECK-LABEL: 'fneg' -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = fneg float undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F32 = fneg <4 x float> undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8F32 = fneg <8 x float> undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16F32 = fneg <16 x float> undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = fneg double undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2F64 = fneg <2 x double> undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F64 = fneg <4 x double> undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8F64 = fneg <8 x double> undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; SSE1-LABEL: 'fneg' +; SSE1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %F32 = fneg float undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4F32 = fneg <4 x float> undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8F32 = fneg <8 x float> undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16F32 = fneg <16 x float> undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %F64 = fneg double undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2F64 = fneg <2 x double> undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V4F64 = fneg <4 x double> undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V8F64 = fneg <8 x double> undef +; SSE1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; +; SSE2-LABEL: 'fneg' +; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = fneg float undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F32 = fneg <4 x float> undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8F32 = fneg <8 x float> undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16F32 = fneg <16 x float> undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = fneg double undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2F64 = fneg <2 x double> undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4F64 = fneg <4 x double> undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8F64 = fneg <8 x double> undef +; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; +; SSE42-LABEL: 'fneg' +; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = fneg float undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F32 = fneg <4 x float> undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8F32 = fneg <8 x float> undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16F32 = fneg <16 x float> undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = fneg double undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2F64 = fneg <2 x double> undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4F64 = fneg <4 x double> undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8F64 = fneg <8 x double> undef +; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; +; AVX-LABEL: 'fneg' +; AVX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = fneg float undef +; AVX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F32 = fneg <4 x float> undef +; AVX-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8F32 = fneg <8 x float> undef +; AVX-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16F32 = fneg <16 x float> undef +; AVX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = fneg double undef +; AVX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2F64 = fneg <2 x double> undef +; AVX-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4F64 = fneg <4 x double> undef +; AVX-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8F64 = fneg <8 x double> undef +; AVX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; +; AVX512-LABEL: 'fneg' +; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = fneg float undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F32 = fneg <4 x float> undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8F32 = fneg <8 x float> undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16F32 = fneg <16 x float> undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = fneg double undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2F64 = fneg <2 x double> undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4F64 = fneg <4 x double> undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8F64 = fneg <8 x double> undef +; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; +; SLM-LABEL: 'fneg' +; SLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = fneg float undef +; SLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F32 = fneg <4 x float> undef +; SLM-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8F32 = fneg <8 x float> undef +; SLM-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16F32 = fneg <16 x float> undef +; SLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = fneg double undef +; SLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2F64 = fneg <2 x double> undef +; SLM-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4F64 = fneg <4 x double> undef +; SLM-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8F64 = fneg <8 x double> undef +; SLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; +; GLM-LABEL: 'fneg' +; GLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = fneg float undef +; GLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F32 = fneg <4 x float> undef +; GLM-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8F32 = fneg <8 x float> undef +; GLM-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16F32 = fneg <16 x float> undef +; GLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F64 = fneg double undef +; GLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2F64 = fneg <2 x double> undef +; GLM-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4F64 = fneg <4 x double> undef +; GLM-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8F64 = fneg <8 x double> undef +; GLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef ; %F32 = fneg float undef %V4F32 = fneg <4 x float> undef diff --git a/llvm/test/Analysis/CostModel/X86/intrinsic-cost-kinds.ll b/llvm/test/Analysis/CostModel/X86/intrinsic-cost-kinds.ll index bd0ad4c..ef7c4fa 100644 --- a/llvm/test/Analysis/CostModel/X86/intrinsic-cost-kinds.ll +++ b/llvm/test/Analysis/CostModel/X86/intrinsic-cost-kinds.ll @@ -134,7 +134,7 @@ define void @fmuladd(float %a, float %b, float %c, <16 x float> %va, <16 x float ; ; LATE-LABEL: 'fmuladd' ; LATE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %s = call float @llvm.fmuladd.f32(float %a, float %b, float %c) -; LATE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v = call <16 x float> @llvm.fmuladd.v16f32(<16 x float> %va, <16 x float> %vb, <16 x float> %vc) +; LATE-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %v = call <16 x float> @llvm.fmuladd.v16f32(<16 x float> %va, <16 x float> %vb, <16 x float> %vc) ; LATE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; SIZE-LABEL: 'fmuladd' @@ -144,7 +144,7 @@ define void @fmuladd(float %a, float %b, float %c, <16 x float> %va, <16 x float ; ; SIZE_LATE-LABEL: 'fmuladd' ; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %s = call float @llvm.fmuladd.f32(float %a, float %b, float %c) -; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v = call <16 x float> @llvm.fmuladd.v16f32(<16 x float> %va, <16 x float> %vb, <16 x float> %vc) +; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %v = call <16 x float> @llvm.fmuladd.v16f32(<16 x float> %va, <16 x float> %vb, <16 x float> %vc) ; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; %s = call float @llvm.fmuladd.f32(float %a, float %b, float %c) -- 2.7.4