From acfb5554c769ad7e09b9e4e42b572cc297a728e9 Mon Sep 17 00:00:00 2001 From: Rodrigo Vivi Date: Wed, 23 Aug 2017 13:35:04 -0700 Subject: [PATCH] drm/i915/cnl: WaForceContextSaveRestoreNonCoherent To avoid a potential hang condition with TLB invalidation we need to enable masked bit 5 of MMIO 0xE5F0 at boot. Same workaround was in place for previous platforms, but the register offset has changed for CNL. But also BSpec doesn't mention the bit 15 as set on gen9 platforms and mark bit as reserved on CNL. v2: Improve commit message accepting Oscar's suggestion. Cc: Mika Kuoppala Cc: Oscar Mateo Signed-off-by: Rodrigo Vivi Reviewed-by: Oscar Mateo Link: https://patchwork.freedesktop.org/patch/msgid/20170823203504.10012-1-rodrigo.vivi@intel.com --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_engine_cs.c | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index d9b0249..c59c590 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7024,6 +7024,7 @@ enum { /* GEN8 chicken */ #define HDC_CHICKEN0 _MMIO(0x7300) +#define CNL_HDC_CHICKEN0 _MMIO(0xE5F0) #define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1<<15) #define HDC_FENCE_DEST_SLM_DISABLE (1<<14) #define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11) diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index d7e1ccf..a6ac9d0 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -1070,6 +1070,10 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine) struct drm_i915_private *dev_priv = engine->i915; int ret; + /* WaForceContextSaveRestoreNonCoherent:cnl */ + WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0, + HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT); + /* WaDisableReplayBufferBankArbitrationOptimization:cnl */ WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); -- 2.7.4