From ac2a1e959690e8e5243db878bfd114b72a8c4be5 Mon Sep 17 00:00:00 2001
From: Nashe Mncube <nashe.mncube@arm.com>
Date: Mon, 8 Mar 2021 09:37:56 +0000
Subject: [PATCH] [SVE] Suppress vselect warning from incorrect interface call

The VSelectCombine handler within AArch64ISelLowering,
uses an interface call which only expects fixed vectors.
This generates a warning when the call is made on a
scalable vector. This warning has been suppressed with this change,
by using the ElementCount interface, which supports both fixed and scalable vectors.
I have also added a regression test which recreates the warning.

Differential Revision: https://reviews.llvm.org/D98249
---
 llvm/lib/Target/AArch64/AArch64ISelLowering.cpp |  3 +-
 llvm/test/CodeGen/AArch64/sve-cmp-select.ll     | 41 +++++++++++++++++++++++++
 2 files changed, 43 insertions(+), 1 deletion(-)
 create mode 100644 llvm/test/CodeGen/AArch64/sve-cmp-select.ll

diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 4275ff7..a40db7e 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -15230,7 +15230,8 @@ static SDValue performVSelectCombine(SDNode *N, SelectionDAG &DAG) {
     }
   }
 
-  if (N0.getOpcode() != ISD::SETCC || CCVT.getVectorNumElements() != 1 ||
+  if (N0.getOpcode() != ISD::SETCC ||
+      CCVT.getVectorElementCount() != ElementCount::getFixed(1) ||
       CCVT.getVectorElementType() != MVT::i1)
     return SDValue();
 
diff --git a/llvm/test/CodeGen/AArch64/sve-cmp-select.ll b/llvm/test/CodeGen/AArch64/sve-cmp-select.ll
new file mode 100644
index 0000000..baaed7a
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/sve-cmp-select.ll
@@ -0,0 +1,41 @@
+; RUN: llc -mtriple=aarch64-linux-unknown -mattr=+sve -o - < %s 2>%t | FileCheck %s
+; RUN: FileCheck --check-prefix="WARN" --allow-empty %s <%t
+
+; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
+; WARN-NOT: warning
+
+define <vscale x 16 x i8> @vselect_cmp_ne(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) {
+  ; CHECK-LABEL: vselect_cmp_ne
+  ; CHECK:       // %bb.0:
+	; CHECK-NEXT:    ptrue	p0.b
+	; CHECK-NEXT:    cmpne	p0.b, p0/z, z0.b, z1.b
+	; CHECK-NEXT:    sel	z0.b, p0, z1.b, z2.b
+	; CHECK-NEXT:    ret
+  %cmp = icmp ne <vscale x 16 x i8> %a, %b
+  %d = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c
+  ret <vscale x 16 x i8> %d
+}
+
+define <vscale x 16 x i8> @vselect_cmp_sgt(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) {
+  ; CHECK-LABEL: vselect_cmp_sgt
+  ; CHECK:       // %bb.0:
+  ; CHECK-NEXT: 	ptrue	p0.b
+  ; CHECK-NEXT: 	cmpgt	p0.b, p0/z, z0.b, z1.b
+  ; CHECK-NEXT: 	sel	z0.b, p0, z1.b, z2.b
+  ; CHECK-NEXT: 	ret
+  %cmp = icmp sgt <vscale x 16 x i8> %a, %b
+  %d = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c
+  ret <vscale x 16 x i8> %d
+}
+
+define <vscale x 16 x i8> @vselect_cmp_ugt(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) {
+  ; CHECK-LABEL: vselect_cmp_ugt
+  ; CHECK:       // %bb.0:
+  ; CHECK-NEXT: 	ptrue	p0.b
+  ; CHECK-NEXT: 	cmphi	p0.b, p0/z, z0.b, z1.b
+  ; CHECK-NEXT: 	sel	z0.b, p0, z1.b, z2.b
+  ; CHECK-NEXT: 	ret
+  %cmp = icmp ugt <vscale x 16 x i8> %a, %b
+  %d = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c
+  ret <vscale x 16 x i8> %d
+}
-- 
2.7.4