From ac21dd4aee450b2a4bc63adb05356b07abba2ff6 Mon Sep 17 00:00:00 2001 From: Matt Turner Date: Mon, 11 Feb 2019 13:41:32 -0800 Subject: [PATCH] intel/compiler/test: Add unit test for mismatched signedness comparison v2 (idr): Move adding the test to after adding the fix. Reordering the two commits prevents possible headaches for git-bisect with scripts that always do 'ninja check'. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109404 Reviewed-by: Ian Romanick --- src/intel/compiler/test_fs_cmod_propagation.cpp | 32 +++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/src/intel/compiler/test_fs_cmod_propagation.cpp b/src/intel/compiler/test_fs_cmod_propagation.cpp index 38bd0de..faabc23 100644 --- a/src/intel/compiler/test_fs_cmod_propagation.cpp +++ b/src/intel/compiler/test_fs_cmod_propagation.cpp @@ -889,3 +889,35 @@ TEST_F(cmod_propagation_test, subtract_delete_compare_derp) EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 1)->opcode); EXPECT_EQ(BRW_PREDICATE_NORMAL, instruction(block0, 1)->predicate); } + +TEST_F(cmod_propagation_test, signed_unsigned_comparison_mismatch) +{ + const fs_builder &bld = v->bld; + fs_reg dest0 = v->vgrf(glsl_type::int_type); + fs_reg src0 = v->vgrf(glsl_type::int_type); + src0.type = BRW_REGISTER_TYPE_W; + + bld.ASR(dest0, negate(src0), brw_imm_d(15)); + bld.CMP(bld.null_reg_ud(), retype(dest0, BRW_REGISTER_TYPE_UD), + brw_imm_ud(0u), BRW_CONDITIONAL_LE); + + /* = Before = + * 0: asr(8) dest:D -src0:W 15D + * 1: cmp.le.f0(8) null:UD dest:UD 0UD + * + * = After = + * (no changes) + */ + v->calculate_cfg(); + bblock_t *block0 = v->cfg->blocks[0]; + + EXPECT_EQ(0, block0->start_ip); + EXPECT_EQ(1, block0->end_ip); + + EXPECT_FALSE(cmod_propagation(v)); + EXPECT_EQ(0, block0->start_ip); + EXPECT_EQ(1, block0->end_ip); + EXPECT_EQ(BRW_OPCODE_ASR, instruction(block0, 0)->opcode); + EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode); + EXPECT_EQ(BRW_CONDITIONAL_LE, instruction(block0, 1)->conditional_mod); +} -- 2.7.4