From ac04923b0f49d943a9a2c8b37cfd0e55aac78505 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Fri, 25 Mar 2016 14:17:54 +0000 Subject: [PATCH] [X86][SSE] Don't duplicate Lower256IntArith functionality in LowerShift. NFC. LowerShift was using the same code as Lower256IntArith to split 256-bit vectors into 2 x 128-bit vectors, so now we just call Lower256IntArith. llvm-svn: 264403 --- llvm/lib/Target/X86/X86ISelLowering.cpp | 22 ++-------------------- 1 file changed, 2 insertions(+), 20 deletions(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index d245b85..a0752b6 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -19897,26 +19897,8 @@ static SDValue LowerShift(SDValue Op, const X86Subtarget &Subtarget, } // Decompose 256-bit shifts into smaller 128-bit shifts. - if (VT.is256BitVector()) { - unsigned NumElems = VT.getVectorNumElements(); - MVT EltVT = VT.getVectorElementType(); - MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); - - // Extract the two vectors - SDValue V1 = extract128BitVector(R, 0, DAG, dl); - SDValue V2 = extract128BitVector(R, NumElems / 2, DAG, dl); - - // Recreate the shift amount vectors - SDValue Amt1 = extract128BitVector(Amt, 0, DAG, dl); - SDValue Amt2 = extract128BitVector(Amt, NumElems / 2, DAG, dl); - - // Issue new vector shifts for the smaller types - V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1); - V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2); - - // Concatenate the result back - return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2); - } + if (VT.is256BitVector()) + return Lower256IntArith(Op, DAG); return SDValue(); } -- 2.7.4