From ac025fd6cb720cd5f1a31cea7751f7206e9f767f Mon Sep 17 00:00:00 2001 From: Andre Vieira Date: Thu, 24 May 2018 08:53:39 +0000 Subject: [PATCH] PR target/83009: Relax strict address checking for store pair lanes The operand constraint for the memory address of store/load pair lanes was enforcing strictly hardware registers be allowed as memory addresses. We want to relax that such that these patterns can be used by combine. During register allocation the register constraint will enforce the correct register is chosen. gcc 2018-05-24 Andre Vieira PR target/83009 * config/aarch64/predicates.md (aarch64_mem_pair_lanes_operand): Make address check not strict. gcc/testsuite 2018-05-24 Andre Vieira PR target/83009 * gcc/target/aarch64/store_v2vec_lanes.c: Add extra tests. From-SVN: r260635 --- gcc/ChangeLog | 6 +++++ gcc/config/aarch64/predicates.md | 2 +- gcc/testsuite/ChangeLog | 5 ++++ .../gcc.target/aarch64/store_v2vec_lanes.c | 28 +++++++++++++++++++--- 4 files changed, 37 insertions(+), 4 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index db2755c..9c7a386 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2018-05-24 Andre Vieira + + PR target/83009 + * config/aarch64/predicates.md (aarch64_mem_pair_lanes_operand): Make + address check not strict. + 2018-05-24 Richard Sandiford * gimple-match.h (gimple_match_op): New class. diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md index 7aec76d..4814b93 100644 --- a/gcc/config/aarch64/predicates.md +++ b/gcc/config/aarch64/predicates.md @@ -226,7 +226,7 @@ ;; as a 128-bit vec_concat. (define_predicate "aarch64_mem_pair_lanes_operand" (and (match_code "mem") - (match_test "aarch64_legitimate_address_p (DFmode, XEXP (op, 0), 1, + (match_test "aarch64_legitimate_address_p (DFmode, XEXP (op, 0), false, ADDR_QUERY_LDP_STP)"))) (define_predicate "aarch64_prefetch_operand" diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index fb4c74e..485cee4 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2018-05-24 Andre Vieira + + PR target/83009 + * gcc/target/aarch64/store_v2vec_lanes.c: Add extra tests. + 2018-05-23 Jozef Lawrynowicz PR target/78849 diff --git a/gcc/testsuite/gcc.target/aarch64/store_v2vec_lanes.c b/gcc/testsuite/gcc.target/aarch64/store_v2vec_lanes.c index 990aea3..3296d04 100644 --- a/gcc/testsuite/gcc.target/aarch64/store_v2vec_lanes.c +++ b/gcc/testsuite/gcc.target/aarch64/store_v2vec_lanes.c @@ -22,10 +22,32 @@ construct_lane_2 (long long *y, v2di *z) z[2] = x; } +void +construct_lane_3 (double **py, v2df **pz) +{ + double *y = *py; + v2df *z = *pz; + double y0 = y[0] + 1; + double y1 = y[1] + 2; + v2df x = {y0, y1}; + z[2] = x; +} + +void +construct_lane_4 (long long **py, v2di **pz) +{ + long long *y = *py; + v2di *z = *pz; + long long y0 = y[0] + 1; + long long y1 = y[1] + 2; + v2di x = {y0, y1}; + z[2] = x; +} + /* We can use the load_pair_lanes pattern to vec_concat two DI/DF values from consecutive memory into a 2-element vector by using a Q-reg LDR. */ -/* { dg-final { scan-assembler-times "stp\td\[0-9\]+, d\[0-9\]+" 1 { xfail ilp32 } } } */ -/* { dg-final { scan-assembler-times "stp\tx\[0-9\]+, x\[0-9\]+" 1 { xfail ilp32 } } } */ -/* { dg-final { scan-assembler-not "ins\t" { xfail ilp32 } } } */ +/* { dg-final { scan-assembler-times "stp\td\[0-9\]+, d\[0-9\]+" 2 } } */ +/* { dg-final { scan-assembler-times "stp\tx\[0-9\]+, x\[0-9\]+" 2 } } */ +/* { dg-final { scan-assembler-not "ins\t" } } */ -- 2.7.4