From ac0244552497848ef2a2e6b69565a4bd6daedf74 Mon Sep 17 00:00:00 2001 From: Simon Tatham Date: Tue, 4 Jun 2019 08:28:48 +0000 Subject: [PATCH] [ARM] Turn some undefined encoding bits into 0s. The family of 32-bit Thumb instruction encodings that include t2ORR, t2AND and t2EOR are all listed in the ArmARM as having (0) in bit 15. The Tablegen descriptions of those instructions listed them as ?. This change tightens that up by making them into 0 + Unpredictable. In the specific case of t2ORR, we tighten it up still further by making the zero bit mandatory. This change comes from Arm v8.1-M, in which encodings with that bit equal to 1 will now be used for different instructions. Reviewers: dmgreen, samparker, SjoerdMeijer, efriedma Reviewed By: dmgreen, efriedma Subscribers: efriedma, javed.absar, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60705 llvm-svn: 362470 --- llvm/lib/Target/ARM/ARMInstrThumb2.td | 17 +++++ llvm/test/MC/Disassembler/ARM/thumb2-bit-15.txt | 92 +++++++++++++++++++++++++ 2 files changed, 109 insertions(+) create mode 100644 llvm/test/MC/Disassembler/ARM/thumb2-bit-15.txt diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td index 234b276..e82cbee 100644 --- a/llvm/lib/Target/ARM/ARMInstrThumb2.td +++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td @@ -603,6 +603,17 @@ multiclass T2I_bin_irs opcod, string opc, let Inst{31-27} = 0b11101; let Inst{26-25} = 0b01; let Inst{24-21} = opcod; + let Inst{15} = 0b0; + // In most of these instructions, and most versions of the Arm + // architecture, bit 15 of this encoding is listed as (0) rather + // than 0, i.e. setting it to 1 is UNPREDICTABLE or a soft-fail + // rather than a hard failure. In v8.1-M, this requirement is + // upgraded to a hard one for ORR, so that the encodings with 1 + // in this bit can be reused for other instructions (such as + // CSEL). Setting Unpredictable{15} = 1 here would reintroduce + // that encoding clash in the auto- generated MC decoder, so I + // comment it out. + let Unpredictable{15} = !if(!eq(opcod, 0b0010), 0b0, 0b1); let Inst{14-12} = 0b000; // imm3 let Inst{7-6} = 0b00; // imm2 let Inst{5-4} = 0b00; // type @@ -616,6 +627,8 @@ multiclass T2I_bin_irs opcod, string opc, let Inst{31-27} = 0b11101; let Inst{26-25} = 0b01; let Inst{24-21} = opcod; + let Inst{15} = 0; + let Unpredictable{15} = !if(!eq(opcod, 0b0010), 0b0, 0b1); // see above } // Assembly aliases for optional destination operand when it's the same // as the source operand. @@ -879,6 +892,7 @@ multiclass T2I_sh_ir opcod, string opc, Operand ty, SDNode opnode> { let Inst{31-27} = 0b11101; let Inst{26-21} = 0b010010; let Inst{19-16} = 0b1111; // Rn + let Inst{15} = 0b0; let Inst{5-4} = opcod; } // register @@ -1872,6 +1886,7 @@ def t2MOVr : T2sTwoReg<(outs GPRnopc:$Rd), (ins GPRnopc:$Rm), IIC_iMOVr, let Inst{26-25} = 0b01; let Inst{24-21} = 0b0010; let Inst{19-16} = 0b1111; // Rn + let Inst{15} = 0b0; let Inst{14-12} = 0b000; let Inst{7-4} = 0b0000; } @@ -2400,6 +2415,8 @@ def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi, let Inst{26-25} = 0b01; let Inst{24-21} = 0b0010; let Inst{19-16} = 0b1111; // Rn + let Inst{15} = 0b0; + let Unpredictable{15} = 0b1; let Inst{14-12} = 0b000; let Inst{7-4} = 0b0011; } diff --git a/llvm/test/MC/Disassembler/ARM/thumb2-bit-15.txt b/llvm/test/MC/Disassembler/ARM/thumb2-bit-15.txt new file mode 100644 index 0000000..a73e7c9 --- /dev/null +++ b/llvm/test/MC/Disassembler/ARM/thumb2-bit-15.txt @@ -0,0 +1,92 @@ +# RUN: not llvm-mc -triple=thumbv7 -mcpu=cortex-a8 -disassemble < %s 2> %t | FileCheck %s +# RUN: FileCheck --check-prefix=ERROR < %t %s + +[0x09,0xea,0x08,0x04] +# CHECK: and.w r4, r9, r8 + +[0x09,0xea,0x08,0x84] +# CHECK: and.w r4, r9, r8 +# ERROR: [[@LINE-2]]:2: warning: potentially undefined instruction encoding + +[0x04,0xea,0xe8,0x01] +# CHECK: and.w r1, r4, r8, asr #3 + +[0x04,0xea,0xe8,0x81] +# CHECK: and.w r1, r4, r8, asr #3 +# ERROR: [[@LINE-2]]:2: warning: potentially undefined instruction encoding + +[0x11,0xea,0x47,0x02] +# CHECK: ands.w r2, r1, r7, lsl #1 + +[0x11,0xea,0x47,0x82] +# CHECK: ands.w r2, r1, r7, lsl #1 +# ERROR: [[@LINE-2]]:2: warning: potentially undefined instruction encoding + +[0x45,0xea,0x06,0x04] +# CHECK: orr.w r4, r5, r6 + +[0x45,0xea,0x06,0x84] +# ERROR: [[@LINE-1]]:2: warning: invalid instruction encoding + +[0x45,0xea,0x46,0x14] +# CHECK: orr.w r4, r5, r6, lsl #5 + +[0x45,0xea,0x46,0x94] +# ERROR: [[@LINE-1]]:2: warning: invalid instruction encoding + +[0x55,0xea,0x56,0x14] +# CHECK: orrs.w r4, r5, r6, lsr #5 + +[0x55,0xea,0x56,0x94] +# ERROR: [[@LINE-1]]:2: warning: invalid instruction encoding + +[0x85,0xea,0x06,0x04] +# CHECK: eor.w r4, r5, r6 + +[0x85,0xea,0x06,0x84] +# CHECK: eor.w r4, r5, r6 +# ERROR: [[@LINE-2]]:2: warning: potentially undefined instruction encoding + +[0x85,0xea,0x46,0x14] +# CHECK: eor.w r4, r5, r6, lsl #5 + +[0x85,0xea,0x46,0x94] +# CHECK: eor.w r4, r5, r6, lsl #5 +# ERROR: [[@LINE-2]]:2: warning: potentially undefined instruction encoding + +[0x4f,0xea,0x02,0x01] +# CHECK: mov.w r1, r2 + +[0x4f,0xea,0x02,0x81] +# ERROR: [[@LINE-1]]:2: warning: invalid instruction encoding + +[0x4f,0xea,0x02,0x46] +# CHECK: lsl.w r6, r2, #16 + +[0x4f,0xea,0x02,0xc6] +# ERROR: [[@LINE-1]]:2: warning: invalid instruction encoding + +[0x4f,0xea,0x12,0x46] +# CHECK: lsr.w r6, r2, #16 + +[0x4f,0xea,0x12,0xc6] +# ERROR: [[@LINE-1]]:2: warning: invalid instruction encoding + +[0x5f,0xea,0x22,0x06] +# CHECK: asrs.w r6, r2, #32 + +[0x5f,0xea,0x22,0x86] +# ERROR: [[@LINE-1]]:2: warning: invalid instruction encoding + +[0x5f,0xea,0x72,0x16] +# CHECK: rors.w r6, r2, #5 + +[0x5f,0xea,0x72,0x96] +# ERROR: [[@LINE-1]]:2: warning: invalid instruction encoding + +[0x4f,0xea,0x34,0x04] +# CHECK: rrx r4, r4 + +[0x4f,0xea,0x34,0x84] +# CHECK: rrx r4, r4 +# ERROR: [[@LINE-2]]:2: warning: potentially undefined instruction encoding -- 2.7.4