From aba4e4d6c1c40ea7b8ba793627b62dc83a47a1d0 Mon Sep 17 00:00:00 2001 From: Jon Roelofs Date: Tue, 14 Mar 2023 17:10:05 -0700 Subject: [PATCH] [AArch64] Add hex comments to mov-imm spellings in the InstPrinter Differential Revision: https://reviews.llvm.org/D146105 --- .../AArch64/MCTargetDesc/AArch64InstPrinter.cpp | 32 ++++++++++++++-------- llvm/test/CodeGen/AArch64/movw-consts.ll | 32 +++++++++++----------- .../Inputs/aarch64_function_name.ll.expected | 4 +-- .../aarch64_generated_funcs.ll.generated.expected | 20 +++++++------- ...aarch64_generated_funcs.ll.nogenerated.expected | 14 +++++----- 5 files changed, 55 insertions(+), 47 deletions(-) diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp index 7c32c6f..2983e9a 100644 --- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp +++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp @@ -282,6 +282,23 @@ void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address, return; } + auto PrintMovImm = [&](uint64_t Value, int RegWidth) { + int64_t SExtVal = SignExtend64(Value, RegWidth); + O << "\tmov\t"; + printRegName(O, MI->getOperand(0).getReg()); + O << ", " << markup(""); + if (CommentStream) { + // Do the opposite to that used for instruction operands. + if (getPrintImmHex()) + *CommentStream << '=' << formatDec(SExtVal) << '\n'; + else { + uint64_t Mask = maskTrailingOnes(RegWidth); + *CommentStream << '=' << formatHex(SExtVal & Mask) << '\n'; + } + } + }; + // MOVZ, MOVN and "ORR wzr, #imm" instructions are aliases for MOV, but their // domains overlap so they need to be prioritized. The chain is "MOVZ lsl #0 > // MOVZ lsl #N > MOVN lsl #0 > MOVN lsl #N > ORR". The highest instruction @@ -295,10 +312,7 @@ void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address, if (AArch64_AM::isMOVZMovAlias(Value, Shift, Opcode == AArch64::MOVZXi ? 64 : 32)) { - O << "\tmov\t"; - printRegName(O, MI->getOperand(0).getReg()); - O << ", " << markup(""); + PrintMovImm(Value, RegWidth); return; } } @@ -312,10 +326,7 @@ void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address, Value = Value & 0xffffffff; if (AArch64_AM::isMOVNMovAlias(Value, Shift, RegWidth)) { - O << "\tmov\t"; - printRegName(O, MI->getOperand(0).getReg()); - O << ", " << markup(""); + PrintMovImm(Value, RegWidth); return; } } @@ -328,10 +339,7 @@ void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address, uint64_t Value = AArch64_AM::decodeLogicalImmediate( MI->getOperand(2).getImm(), RegWidth); if (!AArch64_AM::isAnyMOVWMovAlias(Value, RegWidth)) { - O << "\tmov\t"; - printRegName(O, MI->getOperand(0).getReg()); - O << ", " << markup(""); + PrintMovImm(Value, RegWidth); return; } } diff --git a/llvm/test/CodeGen/AArch64/movw-consts.ll b/llvm/test/CodeGen/AArch64/movw-consts.ll index d585f74..a351f0d 100644 --- a/llvm/test/CodeGen/AArch64/movw-consts.ll +++ b/llvm/test/CodeGen/AArch64/movw-consts.ll @@ -13,7 +13,7 @@ define i64 @test0() { define i64 @test1() { ; CHECK-LABEL: test1: ; CHECK: ; %bb.0: -; CHECK-NEXT: mov w0, #1 +; CHECK-NEXT: mov w0, #1 ; =0x1 ; CHECK-NEXT: ret ret i64 1 } @@ -21,7 +21,7 @@ define i64 @test1() { define i64 @test2() { ; CHECK-LABEL: test2: ; CHECK: ; %bb.0: -; CHECK-NEXT: mov w0, #65535 +; CHECK-NEXT: mov w0, #65535 ; =0xffff ; CHECK-NEXT: ret ret i64 65535 } @@ -29,7 +29,7 @@ define i64 @test2() { define i64 @test3() { ; CHECK-LABEL: test3: ; CHECK: ; %bb.0: -; CHECK-NEXT: mov w0, #65536 +; CHECK-NEXT: mov w0, #65536 ; =0x10000 ; CHECK-NEXT: ret ret i64 65536 } @@ -37,7 +37,7 @@ define i64 @test3() { define i64 @test4() { ; CHECK-LABEL: test4: ; CHECK: ; %bb.0: -; CHECK-NEXT: mov w0, #-65536 +; CHECK-NEXT: mov w0, #-65536 ; =0xffff0000 ; CHECK-NEXT: ret ret i64 4294901760 } @@ -45,7 +45,7 @@ define i64 @test4() { define i64 @test5() { ; CHECK-LABEL: test5: ; CHECK: ; %bb.0: -; CHECK-NEXT: mov x0, #4294967296 +; CHECK-NEXT: mov x0, #4294967296 ; =0x100000000 ; CHECK-NEXT: ret ret i64 4294967296 } @@ -53,7 +53,7 @@ define i64 @test5() { define i64 @test6() { ; CHECK-LABEL: test6: ; CHECK: ; %bb.0: -; CHECK-NEXT: mov x0, #281470681743360 +; CHECK-NEXT: mov x0, #281470681743360 ; =0xffff00000000 ; CHECK-NEXT: ret ret i64 281470681743360 } @@ -61,7 +61,7 @@ define i64 @test6() { define i64 @test7() { ; CHECK-LABEL: test7: ; CHECK: ; %bb.0: -; CHECK-NEXT: mov x0, #281474976710656 +; CHECK-NEXT: mov x0, #281474976710656 ; =0x1000000000000 ; CHECK-NEXT: ret ret i64 281474976710656 } @@ -71,7 +71,7 @@ define i64 @test7() { define i64 @test8() { ; CHECK-LABEL: test8: ; CHECK: ; %bb.0: -; CHECK-NEXT: mov w0, #-60876 +; CHECK-NEXT: mov w0, #-60876 ; =0xffff1234 ; CHECK-NEXT: ret ret i64 4294906420 } @@ -79,7 +79,7 @@ define i64 @test8() { define i64 @test9() { ; CHECK-LABEL: test9: ; CHECK: ; %bb.0: -; CHECK-NEXT: mov x0, #-1 +; CHECK-NEXT: mov x0, #-1 ; =0xffffffffffffffff ; CHECK-NEXT: ret ret i64 -1 } @@ -87,7 +87,7 @@ define i64 @test9() { define i64 @test10() { ; CHECK-LABEL: test10: ; CHECK: ; %bb.0: -; CHECK-NEXT: mov x0, #-3989504001 +; CHECK-NEXT: mov x0, #-3989504001 ; =0xffffffff1234ffff ; CHECK-NEXT: ret ret i64 18446744069720047615 } @@ -110,7 +110,7 @@ define void @test12() { ; CHECK-LABEL: test12: ; CHECK: ; %bb.0: ; CHECK-NEXT: adrp x8, _var32@PAGE -; CHECK-NEXT: mov w9, #1 +; CHECK-NEXT: mov w9, #1 ; =0x1 ; CHECK-NEXT: str w9, [x8, _var32@PAGEOFF] ; CHECK-NEXT: ret store i32 1, ptr @var32 @@ -121,7 +121,7 @@ define void @test13() { ; CHECK-LABEL: test13: ; CHECK: ; %bb.0: ; CHECK-NEXT: adrp x8, _var32@PAGE -; CHECK-NEXT: mov w9, #65535 +; CHECK-NEXT: mov w9, #65535 ; =0xffff ; CHECK-NEXT: str w9, [x8, _var32@PAGEOFF] ; CHECK-NEXT: ret store i32 65535, ptr @var32 @@ -132,7 +132,7 @@ define void @test14() { ; CHECK-LABEL: test14: ; CHECK: ; %bb.0: ; CHECK-NEXT: adrp x8, _var32@PAGE -; CHECK-NEXT: mov w9, #65536 +; CHECK-NEXT: mov w9, #65536 ; =0x10000 ; CHECK-NEXT: str w9, [x8, _var32@PAGEOFF] ; CHECK-NEXT: ret store i32 65536, ptr @var32 @@ -143,7 +143,7 @@ define void @test15() { ; CHECK-LABEL: test15: ; CHECK: ; %bb.0: ; CHECK-NEXT: adrp x8, _var32@PAGE -; CHECK-NEXT: mov w9, #-65536 +; CHECK-NEXT: mov w9, #-65536 ; =0xffff0000 ; CHECK-NEXT: str w9, [x8, _var32@PAGEOFF] ; CHECK-NEXT: ret store i32 4294901760, ptr @var32 @@ -154,7 +154,7 @@ define void @test16() { ; CHECK-LABEL: test16: ; CHECK: ; %bb.0: ; CHECK-NEXT: adrp x8, _var32@PAGE -; CHECK-NEXT: mov w9, #-1 +; CHECK-NEXT: mov w9, #-1 ; =0xffffffff ; CHECK-NEXT: str w9, [x8, _var32@PAGEOFF] ; CHECK-NEXT: ret store i32 -1, ptr @var32 @@ -164,7 +164,7 @@ define void @test16() { define i64 @test17() { ; CHECK-LABEL: test17: ; CHECK: ; %bb.0: -; CHECK-NEXT: mov x0, #-3 +; CHECK-NEXT: mov x0, #-3 ; =0xfffffffffffffffd ; CHECK-NEXT: ret ; Mustn't MOVN w0 here. diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/aarch64_function_name.ll.expected b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/aarch64_function_name.ll.expected index 61a02b5..8367156 100644 --- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/aarch64_function_name.ll.expected +++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/aarch64_function_name.ll.expected @@ -7,12 +7,12 @@ define hidden i32 @"_Z54bar$ompvariant$bar"() { ; LINUX-LABEL: _Z54bar$ompvariant$bar: ; LINUX: // %bb.0: // %entry -; LINUX-NEXT: mov w0, #2 +; LINUX-NEXT: mov w0, #2 // =0x2 ; LINUX-NEXT: ret ; ; DARWIN-LABEL: _Z54bar$ompvariant$bar: ; DARWIN: ; %bb.0: ; %entry -; DARWIN-NEXT: mov w0, #2 +; DARWIN-NEXT: mov w0, #2 ; =0x2 ; DARWIN-NEXT: ret entry: ret i32 2 diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/aarch64_generated_funcs.ll.generated.expected b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/aarch64_generated_funcs.ll.generated.expected index 92e3485..a75abf4 100644 --- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/aarch64_generated_funcs.ll.generated.expected +++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/aarch64_generated_funcs.ll.generated.expected @@ -71,7 +71,7 @@ attributes #0 = { noredzone nounwind ssp uwtable "frame-pointer"="all" } ; CHECK-NEXT: .cfi_def_cfa w29, 16 ; CHECK-NEXT: .cfi_offset w30, -8 ; CHECK-NEXT: .cfi_offset w29, -16 -; CHECK-NEXT: mov w8, #1 +; CHECK-NEXT: mov w8, #1 // =0x1 ; CHECK-NEXT: stur xzr, [x29, #-8] ; CHECK-NEXT: cbz wzr, .LBB0_3 ; CHECK-NEXT: // %bb.1: @@ -79,7 +79,7 @@ attributes #0 = { noredzone nounwind ssp uwtable "frame-pointer"="all" } ; CHECK-NEXT: ldur w8, [x29, #-8] ; CHECK-NEXT: cbz w8, .LBB0_4 ; CHECK-NEXT: .LBB0_2: -; CHECK-NEXT: mov w8, #1 +; CHECK-NEXT: mov w8, #1 // =0x1 ; CHECK-NEXT: str w8, [sp, #16] ; CHECK-NEXT: b .LBB0_5 ; CHECK-NEXT: .LBB0_3: @@ -87,7 +87,7 @@ attributes #0 = { noredzone nounwind ssp uwtable "frame-pointer"="all" } ; CHECK-NEXT: ldur w8, [x29, #-8] ; CHECK-NEXT: cbnz w8, .LBB0_2 ; CHECK-NEXT: .LBB0_4: -; CHECK-NEXT: mov w8, #1 +; CHECK-NEXT: mov w8, #1 // =0x1 ; CHECK-NEXT: bl OUTLINED_FUNCTION_0 ; CHECK-NEXT: .LBB0_5: ; CHECK-NEXT: mov w0, wzr @@ -108,13 +108,13 @@ attributes #0 = { noredzone nounwind ssp uwtable "frame-pointer"="all" } ; CHECK-NEXT: .cfi_def_cfa w29, 16 ; CHECK-NEXT: .cfi_offset w30, -8 ; CHECK-NEXT: .cfi_offset w29, -16 -; CHECK-NEXT: mov w8, #1 +; CHECK-NEXT: mov w8, #1 // =0x1 ; CHECK-NEXT: adrp x9, x -; CHECK-NEXT: mov w10, #2 -; CHECK-NEXT: mov w11, #3 +; CHECK-NEXT: mov w10, #2 // =0x2 +; CHECK-NEXT: mov w11, #3 // =0x3 ; CHECK-NEXT: mov w0, wzr ; CHECK-NEXT: str w8, [x9, :lo12:x] -; CHECK-NEXT: mov w9, #4 +; CHECK-NEXT: mov w9, #4 // =0x4 ; CHECK-NEXT: stp w8, wzr, [x29, #-8] ; CHECK-NEXT: stur w10, [x29, #-12] ; CHECK-NEXT: stp w9, w11, [sp, #12] @@ -132,9 +132,9 @@ attributes #0 = { noredzone nounwind ssp uwtable "frame-pointer"="all" } ; ; CHECK-LABEL: OUTLINED_FUNCTION_0: ; CHECK: // %bb.0: -; CHECK-NEXT: mov w9, #2 -; CHECK-NEXT: mov w10, #3 -; CHECK-NEXT: mov w11, #4 +; CHECK-NEXT: mov w9, #2 // =0x2 +; CHECK-NEXT: mov w10, #3 // =0x3 +; CHECK-NEXT: mov w11, #4 // =0x4 ; CHECK-NEXT: stp w9, w8, [x29, #-12] ; CHECK-NEXT: stp w11, w10, [sp, #12] ; CHECK-NEXT: ret diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/aarch64_generated_funcs.ll.nogenerated.expected b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/aarch64_generated_funcs.ll.nogenerated.expected index c59b24f..01dd58d 100644 --- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/aarch64_generated_funcs.ll.nogenerated.expected +++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/aarch64_generated_funcs.ll.nogenerated.expected @@ -12,7 +12,7 @@ define dso_local i32 @check_boundaries() #0 { ; CHECK-NEXT: .cfi_def_cfa w29, 16 ; CHECK-NEXT: .cfi_offset w30, -8 ; CHECK-NEXT: .cfi_offset w29, -16 -; CHECK-NEXT: mov w8, #1 +; CHECK-NEXT: mov w8, #1 // =0x1 ; CHECK-NEXT: stur xzr, [x29, #-8] ; CHECK-NEXT: cbz wzr, .LBB0_3 ; CHECK-NEXT: // %bb.1: @@ -20,7 +20,7 @@ define dso_local i32 @check_boundaries() #0 { ; CHECK-NEXT: ldur w8, [x29, #-8] ; CHECK-NEXT: cbz w8, .LBB0_4 ; CHECK-NEXT: .LBB0_2: -; CHECK-NEXT: mov w8, #1 +; CHECK-NEXT: mov w8, #1 // =0x1 ; CHECK-NEXT: str w8, [sp, #16] ; CHECK-NEXT: b .LBB0_5 ; CHECK-NEXT: .LBB0_3: @@ -28,7 +28,7 @@ define dso_local i32 @check_boundaries() #0 { ; CHECK-NEXT: ldur w8, [x29, #-8] ; CHECK-NEXT: cbnz w8, .LBB0_2 ; CHECK-NEXT: .LBB0_4: -; CHECK-NEXT: mov w8, #1 +; CHECK-NEXT: mov w8, #1 // =0x1 ; CHECK-NEXT: bl OUTLINED_FUNCTION_0 ; CHECK-NEXT: .LBB0_5: ; CHECK-NEXT: mov w0, wzr @@ -85,13 +85,13 @@ define dso_local i32 @main() #0 { ; CHECK-NEXT: .cfi_def_cfa w29, 16 ; CHECK-NEXT: .cfi_offset w30, -8 ; CHECK-NEXT: .cfi_offset w29, -16 -; CHECK-NEXT: mov w8, #1 +; CHECK-NEXT: mov w8, #1 // =0x1 ; CHECK-NEXT: adrp x9, x -; CHECK-NEXT: mov w10, #2 -; CHECK-NEXT: mov w11, #3 +; CHECK-NEXT: mov w10, #2 // =0x2 +; CHECK-NEXT: mov w11, #3 // =0x3 ; CHECK-NEXT: mov w0, wzr ; CHECK-NEXT: str w8, [x9, :lo12:x] -; CHECK-NEXT: mov w9, #4 +; CHECK-NEXT: mov w9, #4 // =0x4 ; CHECK-NEXT: stp w8, wzr, [x29, #-8] ; CHECK-NEXT: stur w10, [x29, #-12] ; CHECK-NEXT: stp w9, w11, [sp, #12] -- 2.7.4