From ab61414260712684d8f75c8550933f24e0d1df22 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Sat, 9 Oct 1999 13:18:48 -0700 Subject: [PATCH] alpha.md (extendsidi2): Turn into a splitter. * alpha.md (extendsidi2): Turn into a splitter. Allow f/f. If TARGET_FIX, allow r/f. Remove cvtlq unspec pattern. (peepholes): Re-enable. From-SVN: r29878 --- gcc/ChangeLog | 6 ++++ gcc/config/alpha/alpha.md | 85 ++++++++++++++++++++++++++--------------------- 2 files changed, 53 insertions(+), 38 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 985530d..0c30fa1 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +Sat Oct 9 13:15:53 1999 Richard Henderson + + * alpha.md (extendsidi2): Turn into a splitter. Allow f/f. + If TARGET_FIX, allow r/f. Remove cvtlq unspec pattern. + (peepholes): Re-enable. + Sat Oct 9 12:18:16 1999 Richard Henderson * Makefile.in (flow.o): Depend on TREE_H. diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md index 4fe909d..caf8306 100644 --- a/gcc/config/alpha/alpha.md +++ b/gcc/config/alpha/alpha.md @@ -27,7 +27,6 @@ ;; 1 cttz ;; 2 insxh ;; 3 mskxh -;; 4 cvtlq ;; 5 cvtql ;; 6 nt_lda ;; @@ -389,23 +388,43 @@ ;; Handle 32-64 bit extension from memory to a floating point register ;; specially, since this ocurrs frequently in int->double conversions. -;; This is done with a define_split after reload converting the plain -;; sign-extension into a load+unspec, which of course results in lds+cvtlq. ;; ;; Note that while we must retain the =f case in the insn for reload's ;; benefit, it should be eliminated after reload, so we should never emit ;; code for that case. But we don't reject the possibility. -(define_insn "extendsidi2" - [(set (match_operand:DI 0 "register_operand" "=r,r,?f") - (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m,m")))] +(define_expand "extendsidi2" + [(set (match_operand:DI 0 "register_operand" "") + (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] "" + "") + +(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=r,r,*f,?*f") + (sign_extend:DI + (match_operand:SI 1 "nonimmediate_operand" "r,m,*f,m")))] + "! TARGET_FIX" + "@ + addl %1,$31,%0 + ldl %0,%1 + cvtlq %1,%0 + lds %0,%1\;cvtlq %0,%0" + [(set_attr "type" "iadd,ild,fadd,fld") + (set_attr "length" "*,*,*,8")]) + +(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=r,r,r,*f,?*f") + (sign_extend:DI + (match_operand:SI 1 "nonimmediate_operand" "r,m,*f,*f,m")))] + "TARGET_FIX" "@ addl %1,$31,%0 ldl %0,%1 + ftois %1,%0 + cvtlq %1,%0 lds %0,%1\;cvtlq %0,%0" - [(set_attr "type" "iadd,ild,fld") - (set_attr "length" "*,*,8")]) + [(set_attr "type" "iadd,ild,ftoi,fadd,fld") + (set_attr "length" "*,*,*,*,8")]) ;; Due to issues with CLASS_CANNOT_CHANGE_SIZE, we cannot use a subreg here. (define_split @@ -413,16 +432,9 @@ (sign_extend:DI (match_operand:SI 1 "memory_operand" "")))] "reload_completed" [(set (match_dup 2) (match_dup 1)) - (set (match_dup 0) (unspec:DI [(match_dup 2)] 4))] + (set (match_dup 0) (sign_extend:DI (match_dup 2)))] "operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]));") -(define_insn "" - [(set (match_operand:DI 0 "register_operand" "=f") - (unspec:DI [(match_operand:SI 1 "register_operand" "f")] 4))] - "" - "cvtlq %1,%0" - [(set_attr "type" "fadd")]) - ;; Do addsi3 the way expand_binop would do if we didn't have one. This ;; generates better code. We have the anonymous addsi3 pattern below in ;; case combine wants to make it. @@ -5407,25 +5419,22 @@ ;; Optimize sign-extension of SImode loads. This shows up in the wake of ;; reload when converting fp->int. -;(define_peephole2 -; [(set (match_operand:SI 0 "register_operand" "=r") -; (match_operand:SI 1 "memory_operand" "m")) -; (set (match_operand:DI 2 "register_operand" "=r") -; (sign_extend:DI (match_dup 0)))] -; "rtx_equal_p (operands[0], operands[2]) -; || reg_dead_p (insn, operands[0])" -; [(set (match_dup 2) -; (sign_extend:DI (match_dup 1)))] -; "") -; -;(define_peephole2 -; [(set (match_operand:SI 0 "register_operand" "=r") -; (match_operand:SI 1 "hard_fp_register_operand" "f")) -; (set (match_operand:DI 2 "register_operand" "=r") -; (sign_extend:DI (match_dup 0)))] -; "TARGET_FIX -; && (rtx_equal_p (operands[0], operands[2]) -; || reg_dead_p (insn, operands[0]))" -; [(set (match_dup 2) -; (sign_extend:DI (match_dup 1)))] -; "") +(define_peephole2 + [(set (match_operand:SI 0 "register_operand" "=r") + (match_operand:SI 1 "memory_operand" "m")) + (set (match_operand:DI 2 "register_operand" "=r") + (sign_extend:DI (match_dup 0)))] + "dead_or_set_p (next_nonnote_insn (insn), operands[0])" + [(set (match_dup 2) + (sign_extend:DI (match_dup 1)))] + "") + +(define_peephole2 + [(set (match_operand:SI 0 "register_operand" "=r") + (match_operand:SI 1 "hard_fp_register_operand" "f")) + (set (match_operand:DI 2 "register_operand" "=r") + (sign_extend:DI (match_dup 0)))] + "TARGET_FIX && dead_or_set_p (next_nonnote_insn (insn), operands[0])" + [(set (match_dup 2) + (sign_extend:DI (match_dup 1)))] + "") -- 2.7.4