From ab2cbb8466f0934e3d6fb30069017986ef89e5db Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Wed, 2 Mar 2022 13:32:18 +0000 Subject: [PATCH] [X86] LowerShiftByScalarVariable - remove 32-bit vXi64 bitcast shift amount handling This was handled generically (and better) by D120553 --- llvm/lib/Target/X86/X86ISelLowering.cpp | 18 ------------------ 1 file changed, 18 deletions(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 6ec80d0..d08458b 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -29338,7 +29338,6 @@ static SDValue LowerShiftByScalarVariable(SDValue Op, SelectionDAG &DAG, SDValue Amt = Op.getOperand(1); unsigned Opcode = Op.getOpcode(); unsigned X86OpcI = getTargetVShiftUniformOpcode(Opcode, false); - unsigned X86OpcV = getTargetVShiftUniformOpcode(Opcode, true); // TODO: Use getSplatSourceVector. if (SDValue BaseShAmt = DAG.getSplatValue(Amt)) { @@ -29401,23 +29400,6 @@ static SDValue LowerShiftByScalarVariable(SDValue Op, SelectionDAG &DAG, } } - // Check cases (mainly 32-bit) where i64 is expanded into high and low parts. - if (VT == MVT::v2i64 && Amt.getOpcode() == ISD::BITCAST && - Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) { - Amt = Amt.getOperand(0); - unsigned Ratio = 64 / Amt.getScalarValueSizeInBits(); - std::vector Vals(Ratio); - for (unsigned i = 0; i != Ratio; ++i) - Vals[i] = Amt.getOperand(i); - for (unsigned i = Ratio, e = Amt.getNumOperands(); i != e; i += Ratio) { - for (unsigned j = 0; j != Ratio; ++j) - if (Vals[j] != Amt.getOperand(i + j)) - return SDValue(); - } - - if (supportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode())) - return DAG.getNode(X86OpcV, dl, VT, R, Op.getOperand(1)); - } return SDValue(); } -- 2.7.4