From ab237f54ca2b826d3b4ad8ae9278e02bc2eec167 Mon Sep 17 00:00:00 2001 From: Illyas Mansoor Date: Tue, 17 Apr 2012 14:35:41 +0530 Subject: [PATCH] intel_scu_ipc: remove PM command synchronization BZ: 32160 In R2 we had added serialization of IPC and PM (s0ix/lpmp3/d0ix) commands since there were fabric errors, those issues were root caused and fixed in SCU hence we no longer require this synchronization. Also adding synchronization may adversly affect IPC communication, since WatchDog keepalive is sent thru and IPC command and if s0ix is in progress the watchdog keep alive timer may get blocked till the s0ix command gets completed and this could take couple of seconds, by which time watch dog could get triggerred. Hence removing this synchronization. Change-Id: I52b91d5c84ee8cc380d13f63cc46fa2017e4e4f2 Signed-off-by: Illyas Mansoor Reviewed-on: http://android.intel.com:8080/43669 Reviewed-by: Martin, LoicX Tested-by: Martin, LoicX Reviewed-by: buildbot Tested-by: buildbot --- arch/x86/platform/intel-mid/intel_soc_pmu.c | 12 ------------ drivers/platform/x86/intel_scu_ipc.c | 19 ------------------- include/linux/intel_mid_pm.h | 4 ---- 3 files changed, 35 deletions(-) diff --git a/arch/x86/platform/intel-mid/intel_soc_pmu.c b/arch/x86/platform/intel-mid/intel_soc_pmu.c index b3538fc..1d8c3b2 100644 --- a/arch/x86/platform/intel-mid/intel_soc_pmu.c +++ b/arch/x86/platform/intel-mid/intel_soc_pmu.c @@ -470,18 +470,6 @@ static inline int pmu_read_interrupt_status(void) return result.pmu_pm_ics_parts.int_status; } -void acquire_scu_ready_sem(void) -{ - if (likely(pmu_initialized)) - down(&mid_pmu_cxt->scu_ready_sem); -} - -void release_scu_ready_sem(void) -{ - if (likely(pmu_initialized)) - up(&mid_pmu_cxt->scu_ready_sem); -} - /*This function is used for programming the wake capable devices*/ static void pmu_prepare_wake(int s0ix_state) { diff --git a/drivers/platform/x86/intel_scu_ipc.c b/drivers/platform/x86/intel_scu_ipc.c index 0ea8d69..d965ba5 100644 --- a/drivers/platform/x86/intel_scu_ipc.c +++ b/drivers/platform/x86/intel_scu_ipc.c @@ -161,7 +161,6 @@ static inline void ipc_command(u32 cmd) /* Send ipc command */ ipcdev.cmd = cmd; INIT_COMPLETION(ipcdev.cmd_complete); - acquire_scu_ready_sem(); /* Revert me: * This is a workaround here for MRFLD, because IPC interrupt for MRFLD @@ -258,7 +257,6 @@ static inline int ipc_wait_interrupt(void) /* Re-enable Deeper C-states beyond C6 */ pm_qos_update_request(qos, PM_QOS_DEFAULT_VALUE); - release_scu_ready_sem(); return ret; } @@ -461,12 +459,6 @@ int intel_scu_ipc_mrstfw_update(u8 *buffer, u32 length) /* Driver copies the 2KB MIP header to SRAM at 0xFFFC0000*/ memcpy_toio(fw_update_base, buffer, 0x800); - /* ipc_command will hold scu_ready_sem - * but there is no call to wait for - * interrupt completioin hence doing here - */ - release_scu_ready_sem(); - /* Driver sends "FW Update" IPC command (CMD_ID 0xFE; MSG_ID 0x02). * Upon receiving this command, SCU will write the 2K MIP header * from 0xFFFC0000 into NAND. @@ -481,12 +473,6 @@ int intel_scu_ipc_mrstfw_update(u8 *buffer, u32 length) mdelay(1); } - /* ipc_command will hold scu_ready_sem - * but there is no call to wait for - * interrupt completioin hence doing here - */ - release_scu_ready_sem(); - /* Driver checks Mailbox status. * If the status is 'BADN', then abort (bad NAND). * If the status is 'IPC_FW_TXLOW', then continue. @@ -1118,7 +1104,6 @@ int intel_scu_ipc_medfw_upgrade(void) if (busy_wait(&mfld_fw_upd) < 0) { ret_val = -1; - release_scu_ready_sem(); goto term; } @@ -1137,7 +1122,6 @@ int intel_scu_ipc_medfw_upgrade(void) if (mb_state == MB_ERROR) { dev_dbg(&ipcdev.pdev->dev, "check_mb_status,error\n"); ret_val = -1; - release_scu_ready_sem(); goto term; } @@ -1159,7 +1143,6 @@ int intel_scu_ipc_medfw_upgrade(void) if (busy_wait(&mfld_fw_upd) < 0) { ret_val = -1; - release_scu_ready_sem(); goto term; } @@ -1171,7 +1154,6 @@ int intel_scu_ipc_medfw_upgrade(void) dev_err(&ipcdev.pdev->dev, "calc_offset_and_length_error,error\n"); ret_val = -1; - release_scu_ready_sem(); goto term; } @@ -1181,7 +1163,6 @@ int intel_scu_ipc_medfw_upgrade(void) "Error processing fw chunk=%s\n", mfld_fw_upd.mb_status); ret_val = -1; - release_scu_ready_sem(); goto term; } else dev_dbg(&ipcdev.pdev->dev, diff --git a/include/linux/intel_mid_pm.h b/include/linux/intel_mid_pm.h index 8f32b27..bc8aca0 100644 --- a/include/linux/intel_mid_pm.h +++ b/include/linux/intel_mid_pm.h @@ -107,8 +107,6 @@ extern int get_target_platform_state(unsigned long *eax); extern int mid_s0ix_enter(int); extern int pmu_set_devices_in_d0i0(void); -extern void acquire_scu_ready_sem(void); -extern void release_scu_ready_sem(void); extern int pmu_pci_set_power_state(struct pci_dev *pdev, pci_power_t state); extern pci_power_t pmu_pci_choose_state(struct pci_dev *pdev); @@ -158,8 +156,6 @@ static inline bool pmu_is_s0ix_in_progress(void) { return false; }; static inline int mid_nc_read32(u32 cmd, u32 *data) { return -ENOSYS; } static inline int mid_nc_write32(u32 cmd, u32 data) { return -ENOSYS; } static inline int pmu_set_devices_in_d0i0(void) { return 0; } -static inline void acquire_scu_ready_sem(void) { return; }; -static inline void release_scu_ready_sem(void) { return; }; static inline void pmu_log_ipc(u32 command) { return; }; static inline void pmu_log_ipc_irq(void) { return; }; static inline int pmu_set_emmc_to_d0i0_atomic(void) { return -ENOSYS; } -- 2.7.4