From a9a1f0ae2f8245057e6ce0994cf5a3fc16bf5e40 Mon Sep 17 00:00:00 2001
From: rth <rth@138bc75d-0d04-0410-961f-82ee72b054a4>
Date: Thu, 20 Dec 2012 18:05:19 +0000
Subject: [PATCH] s390: Generate rxsbg, and shifted forms of rosbg

        * config/s390/s390.md (IXOR): New code iterator.
        (*r<IXOR>sbg_<GPR>_noshift): Rename from *insv<GPR>_or_z10_noshift;
        macro-ize to handle XOR too.
        (*r<IXOR>sbg_di_rotl, *r<IXOR>sbg_<GPR>_srl, *r<IXOR>sbg_<GPR>_sll):
        New patterns.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@194645 138bc75d-0d04-0410-961f-82ee72b054a4
---
 gcc/ChangeLog           |  8 ++++++-
 gcc/config/s390/s390.md | 61 ++++++++++++++++++++++++++++++++++++++++++++-----
 2 files changed, 62 insertions(+), 7 deletions(-)

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d2b9342..b01203f 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -28,7 +28,13 @@
 	(*extzv<GPR>_zEC12, *extzv<GPR>_z10): New insns.
 	(*pre_z10_extzv<GPR>): Rename from *extzv<GPR>; simplify with
 	nonzero_shift_count_operand.
-	(*extzv_<mode>_srl, *extzv_<mode>_sll): New insns.
+	(*extzv_<GPR>_srl, *extzv_<GPR>_sll): New insns.
+
+	* config/s390/s390.md (IXOR): New code iterator.
+	(*r<IXOR>sbg_<GPR>_noshift): Rename from *insv<GPR>_or_z10_noshift;
+	macro-ize to handle XOR too.
+	(*r<IXOR>sbg_di_rotl, *r<IXOR>sbg_<GPR>_srl, *r<IXOR>sbg_<GPR>_sll):
+	New patterns.
 
 2012-12-20  Thomas Schwinge  <thomas@codesourcery.com>
 
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index f32004c..3a1b4c0 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -393,6 +393,9 @@
 ;; the same template.
 (define_code_iterator SHIFT [ashift lshiftrt])
 
+;; This iterator allow r[ox]sbg to be defined with the same template
+(define_code_iterator IXOR [ior xor])
+
 ;; This iterator and attribute allow to combine most atomic operations.
 (define_code_iterator ATOMIC [and ior xor plus minus mult])
 (define_code_iterator ATOMIC_Z196 [and ior xor plus])
@@ -3474,15 +3477,61 @@
   [(set_attr "op_type" "RIE")
    (set_attr "z10prop" "z10_super_E1")])
 
-; and op1 with a mask being 1 for the selected bits and 0 for the rest
-(define_insn "*insv<mode>_or_z10_noshift"
+(define_insn "*r<noxa>sbg_<mode>_noshift"
   [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
-	(ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
-			  (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
-		(match_operand:GPR 3 "nonimmediate_operand" "0")))
+	(IXOR:GPR
+	  (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
+                   (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
+	  (match_operand:GPR 3 "nonimmediate_operand" "0")))
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_Z10"
-  "rosbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
+  "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
+  [(set_attr "op_type" "RIE")])
+
+(define_insn "*r<noxa>sbg_di_rotl"
+  [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
+	(IXOR:DI
+	  (and:DI
+	    (rotate:DI
+	      (match_operand:DI 1 "nonimmediate_operand" "d")
+              (match_operand:DI 3 "const_int_operand" ""))
+            (match_operand:DI 2 "contiguous_bitmask_operand" ""))
+	  (match_operand:DI 4 "nonimmediate_operand" "0")))
+   (clobber (reg:CC CC_REGNUM))]
+  "TARGET_Z10"
+  "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%b3"
+  [(set_attr "op_type" "RIE")])
+
+(define_insn "*r<noxa>sbg_<mode>_srl"
+  [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
+	(IXOR:GPR
+	  (and:GPR
+	    (lshiftrt:GPR
+              (match_operand:GPR 1 "nonimmediate_operand" "d")
+              (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
+            (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
+	  (match_operand:GPR 4 "nonimmediate_operand" "0")))
+   (clobber (reg:CC CC_REGNUM))]
+  "TARGET_Z10
+   && s390_extzv_shift_ok (<bitsize>, 64 - INTVAL (operands[3]),
+                           INTVAL (operands[2]))"
+  "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,64-%3"
+  [(set_attr "op_type" "RIE")])
+
+(define_insn "*r<noxa>sbg_<mode>_sll"
+  [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
+	(IXOR:GPR
+	  (and:GPR
+	    (ashift:GPR
+              (match_operand:GPR 1 "nonimmediate_operand" "d")
+              (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
+            (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
+	  (match_operand:GPR 4 "nonimmediate_operand" "0")))
+   (clobber (reg:CC CC_REGNUM))]
+  "TARGET_Z10
+   && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[3]),
+                           INTVAL (operands[2]))"
+  "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3"
   [(set_attr "op_type" "RIE")])
 
 (define_insn "*insv<mode>_mem_reg"
-- 
2.7.4