From a99d0fcad58096ac9a4d037bac1bd2f3da9f66ef Mon Sep 17 00:00:00 2001 From: Heesub Shin Date: Wed, 13 Sep 2017 16:02:17 +0900 Subject: [PATCH] s5j/serial: fix RX availability check UFSTAT[7:0] holds the number of data in Rx FIFO, but zero when Rx FIFO is full. Thus, we need additional check on UFSTAT[8] bit to ensure that the FIFO is empty, if the count is zero. Otherwise, up_rxavailable() may return 'false' even when Rx FIFO is full, though it is less likely to happen. Change-Id: Iffd65bf356dd840e864553daf8aa9a7f04a0368e Signed-off-by: Heesub Shin --- os/arch/arm/src/s5j/s5j_serial.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/os/arch/arm/src/s5j/s5j_serial.c b/os/arch/arm/src/s5j/s5j_serial.c index 77594b3..089ed7a 100644 --- a/os/arch/arm/src/s5j/s5j_serial.c +++ b/os/arch/arm/src/s5j/s5j_serial.c @@ -631,7 +631,8 @@ static bool up_rxavailable(struct uart_dev_s *dev) struct up_dev_s *priv = (struct up_dev_s *)dev->priv; uint32_t ufstat = uart_getreg32(priv, S5J_UART_UFSTAT_OFFSET); - return !!(ufstat & UART_UFSTAT_RX_FIFO_COUNT_MASK); + return !!(ufstat & UART_UFSTAT_RX_FIFO_COUNT_MASK) || + (ufstat & UART_UFSTAT_RX_FIFO_FULL_MASK); } /**************************************************************************** -- 2.7.4