From a993859335c0ec1a38d412b90ecac58e9f3cfdc7 Mon Sep 17 00:00:00 2001 From: Diana Picus Date: Thu, 19 Oct 2017 08:50:28 +0000 Subject: [PATCH] [ARM GlobalISel] Remove redundant tests These test cases don't really add anything that isn't covered by other tests as well, so we can safely remove them. llvm-svn: 316154 --- .../ARM/GlobalISel/arm-instruction-select.mir | 294 ------------------ .../ARM/GlobalISel/arm-regbankselect.mir | 254 --------------- 2 files changed, 548 deletions(-) diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir index 7d8e58ec7f53..7e5e8c3e26c1 100644 --- a/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir +++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir @@ -9,19 +9,13 @@ define void @test_trunc_s32_16() { ret void } - define void @test_add_s8() { ret void } - define void @test_add_s16() { ret void } define void @test_add_s32() { ret void } define void @test_fadd_s32() #0 { ret void } define void @test_fadd_s64() #0 { ret void } - define void @test_sub_s8() { ret void } - define void @test_sub_s16() { ret void } define void @test_sub_s32() { ret void } - define void @test_mul_s8() #1 { ret void } - define void @test_mul_s16() #1 { ret void } define void @test_mul_s32() #1 { ret void } define void @test_mulv5_s32() { ret void } @@ -244,102 +238,6 @@ body: | ; CHECK: BX_RET 14, _, implicit %r0 ... --- -name: test_add_s8 -# CHECK-LABEL: name: test_add_s8 -legalized: true -regBankSelected: true -selected: false -# CHECK: selected: true -registers: - - { id: 0, class: gprb } - - { id: 1, class: gprb } - - { id: 2, class: gprb } - - { id: 3, class: gprb } - - { id: 4, class: gprb } - - { id: 5, class: gprb } -# CHECK-DAG: id: 0, class: gpr -# CHECK-DAG: id: 1, class: gpr -# CHECK-DAG: id: 2, class: gpr -# CHECK-DAG: id: 3, class: gpr -# CHECK-DAG: id: 4, class: gpr -# CHECK-DAG: id: 5, class: gpr -body: | - bb.0: - liveins: %r0, %r1 - - %0(s8) = COPY %r0 - ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0 - - %1(s8) = COPY %r1 - ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1 - - %2(s32) = G_ANYEXT %0(s8) - ; CHECK: [[VREGXEXT:%[0-9]+]] = COPY [[VREGX]] - - %3(s32) = G_ANYEXT %1(s8) - ; CHECK: [[VREGYEXT:%[0-9]+]] = COPY [[VREGY]] - - %4(s32) = G_ADD %2, %3 - ; CHECK: [[VREGSUM:%[0-9]+]] = ADDrr [[VREGXEXT]], [[VREGYEXT]], 14, _, _ - - %5(s8) = G_TRUNC %4(s32) - ; CHECK: [[VREGSUMTR:%[0-9]+]] = COPY [[VREGSUM]] - - %r0 = COPY %5(s8) - ; CHECK: %r0 = COPY [[VREGSUMTR]] - - BX_RET 14, _, implicit %r0 - ; CHECK: BX_RET 14, _, implicit %r0 -... ---- -name: test_add_s16 -# CHECK-LABEL: name: test_add_s16 -legalized: true -regBankSelected: true -selected: false -# CHECK: selected: true -registers: - - { id: 0, class: gprb } - - { id: 1, class: gprb } - - { id: 2, class: gprb } - - { id: 3, class: gprb } - - { id: 4, class: gprb } - - { id: 5, class: gprb } -# CHECK-DAG: id: 0, class: gpr -# CHECK-DAG: id: 1, class: gpr -# CHECK-DAG: id: 2, class: gpr -# CHECK-DAG: id: 3, class: gpr -# CHECK-DAG: id: 4, class: gpr -# CHECK-DAG: id: 5, class: gpr -body: | - bb.0: - liveins: %r0, %r1 - - %0(s16) = COPY %r0 - ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0 - - %1(s16) = COPY %r1 - ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1 - - %2(s32) = G_ANYEXT %0(s16) - ; CHECK: [[VREGXEXT:%[0-9]+]] = COPY [[VREGX]] - - %3(s32) = G_ANYEXT %1(s16) - ; CHECK: [[VREGYEXT:%[0-9]+]] = COPY [[VREGY]] - - %4(s32) = G_ADD %2, %3 - ; CHECK: [[VREGSUM:%[0-9]+]] = ADDrr [[VREGXEXT]], [[VREGYEXT]], 14, _, _ - - %5(s16) = G_TRUNC %4(s32) - ; CHECK: [[VREGSUMTR:%[0-9]+]] = COPY [[VREGSUM]] - - %r0 = COPY %5(s16) - ; CHECK: %r0 = COPY [[VREGSUMTR]] - - BX_RET 14, _, implicit %r0 - ; CHECK: BX_RET 14, _, implicit %r0 -... ---- name: test_add_s32 # CHECK-LABEL: name: test_add_s32 legalized: true @@ -439,102 +337,6 @@ body: | ; CHECK: BX_RET 14, _, implicit %d0 ... --- -name: test_sub_s8 -# CHECK-LABEL: name: test_sub_s8 -legalized: true -regBankSelected: true -selected: false -# CHECK: selected: true -registers: - - { id: 0, class: gprb } - - { id: 1, class: gprb } - - { id: 2, class: gprb } - - { id: 3, class: gprb } - - { id: 4, class: gprb } - - { id: 5, class: gprb } -# CHECK-DAG: id: 0, class: gpr -# CHECK-DAG: id: 1, class: gpr -# CHECK-DAG: id: 2, class: gpr -# CHECK-DAG: id: 3, class: gpr -# CHECK-DAG: id: 4, class: gpr -# CHECK-DAG: id: 5, class: gpr -body: | - bb.0: - liveins: %r0, %r1 - - %0(s8) = COPY %r0 - ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0 - - %1(s8) = COPY %r1 - ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1 - - %2(s32) = G_ANYEXT %0(s8) - ; CHECK: [[VREGXEXT:%[0-9]+]] = COPY [[VREGX]] - - %3(s32) = G_ANYEXT %1(s8) - ; CHECK: [[VREGYEXT:%[0-9]+]] = COPY [[VREGY]] - - %4(s32) = G_SUB %2, %3 - ; CHECK: [[VREGRES:%[0-9]+]] = SUBrr [[VREGXEXT]], [[VREGYEXT]], 14, _, _ - - %5(s8) = G_TRUNC %4(s32) - ; CHECK: [[VREGRESTR:%[0-9]+]] = COPY [[VREGRES]] - - %r0 = COPY %5(s8) - ; CHECK: %r0 = COPY [[VREGRESTR]] - - BX_RET 14, _, implicit %r0 - ; CHECK: BX_RET 14, _, implicit %r0 -... ---- -name: test_sub_s16 -# CHECK-LABEL: name: test_sub_s16 -legalized: true -regBankSelected: true -selected: false -# CHECK: selected: true -registers: - - { id: 0, class: gprb } - - { id: 1, class: gprb } - - { id: 2, class: gprb } - - { id: 3, class: gprb } - - { id: 4, class: gprb } - - { id: 5, class: gprb } -# CHECK-DAG: id: 0, class: gpr -# CHECK-DAG: id: 1, class: gpr -# CHECK-DAG: id: 2, class: gpr -# CHECK-DAG: id: 3, class: gpr -# CHECK-DAG: id: 4, class: gpr -# CHECK-DAG: id: 5, class: gpr -body: | - bb.0: - liveins: %r0, %r1 - - %0(s16) = COPY %r0 - ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0 - - %1(s16) = COPY %r1 - ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1 - - %2(s32) = G_ANYEXT %0(s16) - ; CHECK: [[VREGXEXT:%[0-9]+]] = COPY [[VREGX]] - - %3(s32) = G_ANYEXT %1(s16) - ; CHECK: [[VREGYEXT:%[0-9]+]] = COPY [[VREGY]] - - %4(s32) = G_SUB %2, %3 - ; CHECK: [[VREGRES:%[0-9]+]] = SUBrr [[VREGXEXT]], [[VREGYEXT]], 14, _, _ - - %5(s16) = G_TRUNC %4(s32) - ; CHECK: [[VREGRESTR:%[0-9]+]] = COPY [[VREGRES]] - - %r0 = COPY %5(s16) - ; CHECK: %r0 = COPY [[VREGRESTR]] - - BX_RET 14, _, implicit %r0 - ; CHECK: BX_RET 14, _, implicit %r0 -... ---- name: test_sub_s32 # CHECK-LABEL: name: test_sub_s32 legalized: true @@ -568,102 +370,6 @@ body: | ; CHECK: BX_RET 14, _, implicit %r0 ... --- -name: test_mul_s8 -# CHECK-LABEL: name: test_mul_s8 -legalized: true -regBankSelected: true -selected: false -# CHECK: selected: true -registers: - - { id: 0, class: gprb } - - { id: 1, class: gprb } - - { id: 2, class: gprb } - - { id: 3, class: gprb } - - { id: 4, class: gprb } - - { id: 5, class: gprb } -# CHECK-DAG: id: 0, class: gpr -# CHECK-DAG: id: 1, class: gpr -# CHECK-DAG: id: 2, class: gprnopc -# CHECK-DAG: id: 3, class: gprnopc -# CHECK-DAG: id: 4, class: gprnopc -# CHECK-DAG: id: 5, class: gpr -body: | - bb.0: - liveins: %r0, %r1 - - %0(s8) = COPY %r0 - ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0 - - %1(s8) = COPY %r1 - ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1 - - %2(s32) = G_ANYEXT %0(s8) - ; CHECK: [[VREGXEXT:%[0-9]+]] = COPY [[VREGX]] - - %3(s32) = G_ANYEXT %1(s8) - ; CHECK: [[VREGYEXT:%[0-9]+]] = COPY [[VREGY]] - - %4(s32) = G_MUL %2, %3 - ; CHECK: [[VREGRES:%[0-9]+]] = MUL [[VREGXEXT]], [[VREGYEXT]], 14, _, _ - - %5(s8) = G_TRUNC %4(s32) - ; CHECK: [[VREGRESTR:%[0-9]+]] = COPY [[VREGRES]] - - %r0 = COPY %5(s8) - ; CHECK: %r0 = COPY [[VREGRESTR]] - - BX_RET 14, _, implicit %r0 - ; CHECK: BX_RET 14, _, implicit %r0 -... ---- -name: test_mul_s16 -# CHECK-LABEL: name: test_mul_s16 -legalized: true -regBankSelected: true -selected: false -# CHECK: selected: true -registers: - - { id: 0, class: gprb } - - { id: 1, class: gprb } - - { id: 2, class: gprb } - - { id: 3, class: gprb } - - { id: 4, class: gprb } - - { id: 5, class: gprb } -# CHECK-DAG: id: 0, class: gpr -# CHECK-DAG: id: 1, class: gpr -# CHECK-DAG: id: 2, class: gprnopc -# CHECK-DAG: id: 3, class: gprnopc -# CHECK-DAG: id: 4, class: gprnopc -# CHECK-DAG: id: 5, class: gpr -body: | - bb.0: - liveins: %r0, %r1 - - %0(s16) = COPY %r0 - ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0 - - %1(s16) = COPY %r1 - ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1 - - %2(s32) = G_ANYEXT %0(s16) - ; CHECK: [[VREGXEXT:%[0-9]+]] = COPY [[VREGX]] - - %3(s32) = G_ANYEXT %1(s16) - ; CHECK: [[VREGYEXT:%[0-9]+]] = COPY [[VREGY]] - - %4(s32) = G_MUL %2, %3 - ; CHECK: [[VREGRES:%[0-9]+]] = MUL [[VREGXEXT]], [[VREGYEXT]], 14, _, _ - - %5(s16) = G_TRUNC %4(s32) - ; CHECK: [[VREGRESTR:%[0-9]+]] = COPY [[VREGRES]] - - %r0 = COPY %5(s16) - ; CHECK: %r0 = COPY [[VREGRESTR]] - - BX_RET 14, _, implicit %r0 - ; CHECK: BX_RET 14, _, implicit %r0 -... ---- name: test_mul_s32 # CHECK-LABEL: name: test_mul_s32 legalized: true diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir index c89547613b2d..069dad2f57d2 100644 --- a/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir +++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir @@ -1,17 +1,8 @@ # RUN: llc -mtriple arm-- -global-isel -run-pass=regbankselect %s -o - | FileCheck %s --- | define void @test_add_s32() { ret void } - define void @test_add_s16() { ret void } - define void @test_add_s8() { ret void } - define void @test_add_s1() { ret void } - define void @test_sub_s32() { ret void } - define void @test_sub_s16() { ret void } - define void @test_sub_s8() { ret void } - define void @test_mul_s32() { ret void } - define void @test_mul_s16() { ret void } - define void @test_mul_s8() { ret void } define void @test_sdiv_s32() #1 { ret void } define void @test_udiv_s32() #1 { ret void } @@ -82,111 +73,6 @@ body: | %r0 = COPY %2(s32) BX_RET 14, _, implicit %r0 -... ---- -name: test_add_s16 -# CHECK-LABEL: name: test_add_s16 -legalized: true -regBankSelected: false -selected: false -# CHECK: registers: -# CHECK: - { id: 0, class: gprb, preferred-register: '' } -# CHECK: - { id: 1, class: gprb, preferred-register: '' } -# CHECK: - { id: 2, class: gprb, preferred-register: '' } -# CHECK: - { id: 3, class: gprb, preferred-register: '' } -# CHECK: - { id: 4, class: gprb, preferred-register: '' } -# CHECK: - { id: 5, class: gprb, preferred-register: '' } - -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - %0(s16) = COPY %r0 - %1(s16) = COPY %r1 - %2(s32) = G_ANYEXT %0(s16) - %3(s32) = G_ANYEXT %1(s16) - %4(s32) = G_ADD %2, %3 - %5(s16) = G_TRUNC %4(s32) - %r0 = COPY %5(s16) - BX_RET 14, _, implicit %r0 - -... ---- -name: test_add_s8 -# CHECK-LABEL: name: test_add_s8 -legalized: true -regBankSelected: false -selected: false -# CHECK: registers: -# CHECK: - { id: 0, class: gprb, preferred-register: '' } -# CHECK: - { id: 1, class: gprb, preferred-register: '' } -# CHECK: - { id: 2, class: gprb, preferred-register: '' } -# CHECK: - { id: 3, class: gprb, preferred-register: '' } -# CHECK: - { id: 4, class: gprb, preferred-register: '' } -# CHECK: - { id: 5, class: gprb, preferred-register: '' } - -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - %0(s8) = COPY %r0 - %1(s8) = COPY %r1 - %2(s32) = G_ANYEXT %0(s8) - %3(s32) = G_ANYEXT %1(s8) - %4(s32) = G_ADD %2, %3 - %5(s8) = G_TRUNC %4(s32) - %r0 = COPY %5(s8) - BX_RET 14, _, implicit %r0 - -... ---- -name: test_add_s1 -# CHECK-LABEL: name: test_add_s1 -legalized: true -regBankSelected: false -selected: false -# CHECK: registers: -# CHECK: - { id: 0, class: gprb, preferred-register: '' } -# CHECK: - { id: 1, class: gprb, preferred-register: '' } -# CHECK: - { id: 2, class: gprb, preferred-register: '' } -# CHECK: - { id: 3, class: gprb, preferred-register: '' } -# CHECK: - { id: 4, class: gprb, preferred-register: '' } -# CHECK: - { id: 5, class: gprb, preferred-register: '' } - -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - %0(s1) = COPY %r0 - %1(s1) = COPY %r1 - %2(s32) = G_ANYEXT %0(s1) - %3(s32) = G_ANYEXT %1(s1) - %4(s32) = G_ADD %2, %3 - %5(s1) = G_TRUNC %4(s32) - %r0 = COPY %5(s1) - BX_RET 14, _, implicit %r0 - ... --- name: test_sub_s32 @@ -213,76 +99,6 @@ body: | %r0 = COPY %2(s32) BX_RET 14, _, implicit %r0 -... ---- -name: test_sub_s16 -# CHECK-LABEL: name: test_sub_s16 -legalized: true -regBankSelected: false -selected: false -# CHECK: registers: -# CHECK: - { id: 0, class: gprb, preferred-register: '' } -# CHECK: - { id: 1, class: gprb, preferred-register: '' } -# CHECK: - { id: 2, class: gprb, preferred-register: '' } -# CHECK: - { id: 3, class: gprb, preferred-register: '' } -# CHECK: - { id: 4, class: gprb, preferred-register: '' } -# CHECK: - { id: 5, class: gprb, preferred-register: '' } - -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - %0(s16) = COPY %r0 - %1(s16) = COPY %r1 - %2(s32) = G_ANYEXT %0(s16) - %3(s32) = G_ANYEXT %1(s16) - %4(s32) = G_SUB %2, %3 - %5(s16) = G_TRUNC %4(s32) - %r0 = COPY %5(s16) - BX_RET 14, _, implicit %r0 - -... ---- -name: test_sub_s8 -# CHECK-LABEL: name: test_sub_s8 -legalized: true -regBankSelected: false -selected: false -# CHECK: registers: -# CHECK: - { id: 0, class: gprb, preferred-register: '' } -# CHECK: - { id: 1, class: gprb, preferred-register: '' } -# CHECK: - { id: 2, class: gprb, preferred-register: '' } -# CHECK: - { id: 3, class: gprb, preferred-register: '' } -# CHECK: - { id: 4, class: gprb, preferred-register: '' } -# CHECK: - { id: 5, class: gprb, preferred-register: '' } - -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - %0(s8) = COPY %r0 - %1(s8) = COPY %r1 - %2(s32) = G_ANYEXT %0(s8) - %3(s32) = G_ANYEXT %1(s8) - %4(s32) = G_SUB %2, %3 - %5(s8) = G_TRUNC %4(s32) - %r0 = COPY %5(s8) - BX_RET 14, _, implicit %r0 - ... --- name: test_mul_s32 @@ -309,76 +125,6 @@ body: | %r0 = COPY %2(s32) BX_RET 14, _, implicit %r0 -... ---- -name: test_mul_s16 -# CHECK-LABEL: name: test_mul_s16 -legalized: true -regBankSelected: false -selected: false -# CHECK: registers: -# CHECK: - { id: 0, class: gprb, preferred-register: '' } -# CHECK: - { id: 1, class: gprb, preferred-register: '' } -# CHECK: - { id: 2, class: gprb, preferred-register: '' } -# CHECK: - { id: 3, class: gprb, preferred-register: '' } -# CHECK: - { id: 4, class: gprb, preferred-register: '' } -# CHECK: - { id: 5, class: gprb, preferred-register: '' } - -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - %0(s16) = COPY %r0 - %1(s16) = COPY %r1 - %2(s32) = G_ANYEXT %0(s16) - %3(s32) = G_ANYEXT %1(s16) - %4(s32) = G_MUL %2, %3 - %5(s16) = G_TRUNC %4(s32) - %r0 = COPY %5(s16) - BX_RET 14, _, implicit %r0 - -... ---- -name: test_mul_s8 -# CHECK-LABEL: name: test_mul_s8 -legalized: true -regBankSelected: false -selected: false -# CHECK: registers: -# CHECK: - { id: 0, class: gprb, preferred-register: '' } -# CHECK: - { id: 1, class: gprb, preferred-register: '' } -# CHECK: - { id: 2, class: gprb, preferred-register: '' } -# CHECK: - { id: 3, class: gprb, preferred-register: '' } -# CHECK: - { id: 4, class: gprb, preferred-register: '' } -# CHECK: - { id: 5, class: gprb, preferred-register: '' } - -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - %0(s8) = COPY %r0 - %1(s8) = COPY %r1 - %2(s32) = G_ANYEXT %0(s8) - %3(s32) = G_ANYEXT %1(s8) - %4(s32) = G_MUL %2, %3 - %5(s8) = G_TRUNC %4(s32) - %r0 = COPY %5(s8) - BX_RET 14, _, implicit %r0 - ... --- name: test_sdiv_s32 -- 2.34.1