From a984da88a35b42f444d1f9eeba77aa520b950d35 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Fri, 11 Jun 2021 12:58:22 +0200 Subject: [PATCH] i386: Fix up *vec_concat_0_1 [PR101007] On Fri, Apr 23, 2021 at 12:53:58PM +0800, Hongtao Liu via Gcc-patches wrote: > -(define_insn "*vec_concatv4si_0" > - [(set (match_operand:V4SI 0 "register_operand" "=v,x") > - (vec_concat:V4SI > - (match_operand:V2SI 1 "nonimmediate_operand" "vm,?!*y") > - (match_operand:V2SI 2 "const0_operand" " C,C")))] > +(define_insn "*vec_concat_0" > + [(set (match_operand:VI124_128 0 "register_operand" "=v,x") > + (vec_concat:VI124_128 > + (match_operand: 1 "nonimmediate_operand" "vm,?!*y") > + (match_operand: 2 "const0_operand" " C,C")))] > "TARGET_SSE2" > "@ > %vmovq\t{%1, %0|%0, %1} > @@ -22154,6 +22157,24 @@ (define_insn "avx_vec_concat" > (set_attr "prefix" "maybe_evex") > (set_attr "mode" "")]) > > +(define_insn_and_split "*vec_concat_0" > + [(set (match_operand:V 0 "register_operand") > + (vec_select:V > + (vec_concat: > + (match_operand:V 1 "nonimmediate_operand") > + (match_operand:V 2 "const0_operand")) > + (match_parallel 3 "movq_parallel" > + [(match_operand 4 "const_int_operand")])))] > + "ix86_pre_reload_split ()" > + "#" > + "&& 1" > + [(set (match_dup 0) > + (vec_concat:V (match_dup 1) (match_dup 5)))] > +{ > + operands[1] = gen_lowpart (mode, operands[1]); > + operands[5] = CONST0_RTX (mode); > +}) This regressed the following testcase with -msse -mno-sse2. The define_insn_and_split splits the permutation into *vec_concat_0 or *vec_concatv2di_0 insns which both have TARGET_SSE2 in their conditions (for the former you can see it above), but the define_insn_and_split matches always when the V mode's condition do, which for V16QI/V8HI/V4SI/V2DI/V4SF modes is always (well, when those modes are valid, which is TARGET_SSE). 2021-06-11 Jakub Jelinek PR target/101007 * config/i386/sse.md (*vec_concat_0_1): Require TARGET_SSE2. * gcc.target/i386/sse-pr101007.c: New test. --- gcc/config/i386/sse.md | 2 +- gcc/testsuite/gcc.target/i386/sse-pr101007.c | 14 ++++++++++++++ 2 files changed, 15 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/i386/sse-pr101007.c diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 8403a07..94296bc 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -22394,7 +22394,7 @@ (match_operand:V 2 "const0_operand")) (match_parallel 3 "movq_parallel" [(match_operand 4 "const_int_operand")])))] - "ix86_pre_reload_split ()" + "TARGET_SSE2 && ix86_pre_reload_split ()" "#" "&& 1" [(set (match_dup 0) diff --git a/gcc/testsuite/gcc.target/i386/sse-pr101007.c b/gcc/testsuite/gcc.target/i386/sse-pr101007.c new file mode 100644 index 0000000..65261d2 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse-pr101007.c @@ -0,0 +1,14 @@ +/* PR target/101007 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse -mno-sse2" } */ + +typedef unsigned __attribute__((__vector_size__ (8))) U; +typedef unsigned __attribute__((__vector_size__ (16))) V; +V v; +U *p; + +void +foo (void) +{ + *p = (U) __builtin_shufflevector ((V)(0 == (V){} >= 0), v, 4, 2); +} -- 2.7.4